tag: chiplets

Many More Hurdles In Heterogeneous Integration
By Laura Peters - 18 Jan, 2024 - Comments: 0

Advanced packaging options continue to stack up in the pursuit of “More than Moore” and higher levels of integration. It has become a place where many high-density interconnects converge, and where many new and familiar problems need to be addressed. The industry’s first foray into fine-pitch multi-die packaging utilized silicon interposers with through-silicon vias (TSVs) to deliver s... » read more

Navigating Heat In Advanced Packaging
By Gregory Haley - 18 Jan, 2024 - Comments: 0

The integration of multiple heterogeneous dies in a package is pivotal for extending Moore’s Law and enhancing performance, power efficiency, and functionality, but it also is raising significant issues over how to manage the thermal load. Advanced packaging provides a way to pack more features and functions into a device, increasingly by stacking various components vertically rather than ... » read more

Chiplet Heterogeneity And Advanced Scheduling With Pipelining
By Technical Paper Link - 12 Jan, 2024 - Comments: 0

A technical paper titled “Inter-Layer Scheduling Space Exploration for Multi-model Inference on Heterogeneous Chiplets” was published by researchers at University of California Irvine. Abstract: "To address increasing compute demand from recent multi-model workloads with heavy models like large language models, we propose to deploy heterogeneous chiplet-based multi-chip module (MCM)-based... » read more

Challenges And Innovations Of HW Security And Trust For Chiplet-Based 2.5D and 3D ICs
By Technical Paper Link - 04 Jan, 2024 - Comments: 0

A technical paper titled “On hardware security and trust for chiplet-based 2.5D and 3D ICs: Challenges and Innovations” was published by researchers at STMicroelectronics Crolles (ST-CROLLES), Département Systèmes et Circuits Intégrés Numériques (DSCIN), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), and Laboratoire Systèm... » read more

Design Space Simulator Of Distributed Multi-Chiplet Manycore Architectures For Comm-Intensive Applications
By Technical Paper Link - 04 Jan, 2024 - Comments: 0

A technical paper titled “Muchisim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems” was published by researchers at Princeton University. Abstract: "Current design-space exploration tools cannot accurately evaluate communication-intensive applications whose execution is data-dependent (e.g., graph analytics and sparse linear algebra) on scale-out manycore sys... » read more

Revolutionizing Automotive Design With Chiplet-Based Architecture
By Reela Samuel - 04 Jan, 2024 - Comments: 0

The global chip market has seen a significant increase in demand for high-performance chips due to the rapid growth of the automotive industry. This growth is primarily driven by the adoption of advanced driver-assistance systems (ADAS), electric vehicles (EVs), and connected cars. These technologies require fast data processing, improved sensor fusion, and better communication capabilities to ... » read more

Environmentally Sustainable FPGAs (Notre Dame, Univ. of Pittsburgh)
By Technical Paper Link - 21 Dec, 2023 - Comments: 0

A new technical paper titled "REFRESH FPGAs: Sustainable FPGA Chiplet Architectures" was published by University of Notre Dame and University of Pittsburgh. Abstract "There is a growing call for greater amounts of increasingly agile computational power for edge and cloud infrastructure to serve the computationally complex needs of ubiquitous computing devices. Thus, an important challenge i... » read more

What You Needed To Know In 2023
By Brian Bailey - 21 Dec, 2023 - Comments: 0

I always use the last blog of the year to review everything published in the Systems & Design and Low Power – High Performance channels of Semiconductor Engineering, the two channels that I write for. It is useful to see what interests you and, as I have found in the past, it is an indicator of where the industry is going. You read about the issues you are facing as designers, and you nee... » read more

Proprietary Vs. Commercial Chiplets
By Ed Sperling - 19 Dec, 2023 - Comments: 0

Large chipmakers are focusing on chiplets as the best path forward for integrating more functions into electronic devices. The challenge now is how to pull the rest of the chip industry along, creating a marketplace for third-party chiplets that can be chosen from a menu using specific criteria that can speed time to market, help to control costs, and behave as reliably as chiplets developed in... » read more

Next-Gen Power Integrity Challenges
By Ed Sperling - 14 Dec, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss power integrity challenges and best practices in designs at 7nm and below, and in 2.5D and 3D-IC packages, with Chip Stratakos, partner, physical design at Microsoft; Mohit Jain, principal engineer at Qualcomm; Thomas Quan, director at TSMC; and Murat Becer, vice president at Ansys. What follows are excerpts of that conversatio... » read more

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