tag: DRAM

Solution To Read Disturbance For Current And Future DRAM Chips at Low Area, Performance And Energy Costs (ETH Zurich et al.)
By Technical Paper Link - 07 Mar, 2025 - Comments: 0

A new technical paper titled "Chronus: Understanding and Securing the Cutting-Edge Industry Solutions to DRAM Read Disturbance" was published by researchers at ETH Zurich, TOBB, and University of Sharjah. Abstract "We 1) present the first rigorous security, performance, energy, and cost analyses of the state-of-the-art on-DRAM-die read disturbance mitigation method, Per Row Activation Count... » read more

Effects Of Reduced Refresh Latency On RowHammer Vulnerability Of DDR4 DRAM Chips
By Technical Paper Link - 04 Mar, 2025 - Comments: 0

A new technical paper titled "Understanding RowHammer Under Reduced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions" was published by researchers at ETH Zurich, TOBB University of Economics and Technology, and University of Sharjah. Abstract "RowHammer is a major read disturbance mechanism in DRAM where repeatedly accessing (hammering) a row of... » read more

SW-HW Co-Design Mitigation To Strengthen ASLR Against Microarchitectural Attacks (MIT)
By Technical Paper Link - 26 Feb, 2025 - Comments: 0

A technical paper titled "Oreo: Protecting ASLR Against Microarchitectural Attacks" was published by researchers at MIT. Abstract "Address Space Layout Randomization (ASLR) is one of the most prominently deployed mitigations against memory corruption attacks. ASLR randomly shuffles program virtual addresses to prevent attackers from knowing the location of program contents in memory. Microa... » read more

Interconnects Approach Tipping Point
By Laura Peters - 20 Feb, 2025 - Comments: 0

As leading devices move to next generation nanosheets for logic, their interconnections are getting squeezed past the point where they can deliver low resistance pathways. The 1nm (10Å) node will have 20nm pitch and larger metal lines, but the interconnect stack already consumes a third of device power and accounts for 75% of the chip's RC delay. Changing this dynamic requires a superior co... » read more

Memory Wall Problem Grows With LLMs
By Katherine Derbyshire - 20 Feb, 2025 - Comments: 0

The growing imbalance between the amount of data that needs to be processed to train large language models (LLMs) and the inability to move that data back and forth fast enough between memories and processors has set off a massive global search for a better and more energy- and cost-efficient solution. Much of this is evident in the numbers. The GPU market is forecast to reach $190 billion in ... » read more

Temporal Variation in DRAM Read Disturbance in DDR4 and HBM2 (ETH Zurich, Rutgers)
By Technical Paper Link - 19 Feb, 2025 - Comments: 0

A new technical paper titled "Variable Read Disturbance: An Experimental Analysis of Temporal Variation in DRAM Read Disturbance" was published by researchers at ETH Zurich and Rutgers University. Abstract "Modern DRAM chips are subject to read disturbance errors. State-of-the-art read disturbance mitigations rely on accurate and exhaustive characterization of the read disturbance threshold... » read more

Rowhammer Mitigation With Adaptive Refresh Management Optimization (KAIST, Sk hynix)
By Technical Paper Link - 12 Feb, 2025 - Comments: 0

A new technical paper titled "Securing DRAM at Scale: ARFM-Driven Row Hammer Defense with Unveiling the Threat of Short tRC Patterns" was published by researchers at KAIST and Sk hynix. Abstract (partial) "To address the issue of powerful row hammer (RH) attacks, our study involved an extensive analysis of the prevalent attack patterns in the field. We discovered a strong correlation betwee... » read more

Processing-Using-DRAM: Attaining High-Performance Via Dynamic Precision Bit-Serial Arithmetic (ETH Zurich, et al.)
By Technical Paper Link - 01 Feb, 2025 - Comments: 0

A new technical paper titled "Proteus: Achieving High-Performance Processing-Using-DRAM via Dynamic Precision Bit-Serial Arithmetic" was published by researchers at ETH Zurich, Cambridge University, Universidad de Córdoba, Univ. of Illinois Urbana-Champaign and NVIDIA Research. Abstract "Processing-using-DRAM (PUD) is a paradigm where the analog operational properties of DRAM structures ... » read more

New Class Of Memory: Managed-Retention Memory or MRM (Microsoft Research)
By Technical Paper Link - 22 Jan, 2025 - Comments: 0

A new technical paper titled "Managed-Retention Memory: A New Class of Memory for the AI Era" was published by researchers at Microsoft. Abstract "AI clusters today are one of the major uses of High Bandwidth Memory (HBM). However, HBM is suboptimal for AI workloads for several reasons. Analysis shows HBM is overprovisioned on write performance, but underprovisioned on density and read band... » read more

Choosing The Right Memory Solution For AI Accelerators
By Tim Messegee - 16 Jan, 2025 - Comments: 0

To meet the increasing demands of AI workloads, memory solutions must deliver ever-increasing performance in bandwidth, capacity, and efficiency. From the training of massive large language models (LLMs) to efficient inference on endpoint devices, choosing the right memory technology is critical for chip designers. This blog explores three leading memory solutions—HBM, LPDDR, and GDDR—and t... » read more

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