SRAM In AI: The Future Of Memory


Experts at the Table — Part 1: Semiconductor Engineering sat down to talk about AI and the latest issues in SRAM with Tony Chan Carusone, CTO at Alphawave Semi; Steve Roddy, chief marketing officer at Quadric; and Jongsin Yun, memory technologist at Siemens EDA. What follows are excerpts of that conversation. Part two of this conversation can be found here and part three is here. [L-R]: ... » read more

The Power Of HBM3 Memory For AI Training Hardware


AI training data sets are constantly growing, driving the need for hardware accelerators capable of handling terabyte-scale bandwidth. Among the array of memory technologies available, High Bandwidth Memory (HBM) has emerged as the memory of choice for AI training hardware, with the most recent generation, HBM3, delivering unrivaled memory bandwidth. Let’s take a closer look at this important... » read more

A Novel Approach To Mitigating RowHammer Attacks And Improving Server Memory System Reliability


A technical paper titled “RAMPART: RowHammer Mitigation and Repair for Server Memory Systems” was published by researchers at Rambus. Abstract: "RowHammer attacks are a growing security and reliability concern for DRAMs and computer systems as they can induce many bit errors that overwhelm error detection and correction capabilities. System-level solutions are needed as process technology... » read more

DRAM Test And Inspection Just Gets Tougher


DRAM manufacturers continue to demand cost-effective solutions for screening and process improvement amid growing concerns over defects and process variability, but meeting that demand is becoming much more difficult with the rollout of faster interfaces and multi-chip packages. DRAM plays a key role in a wide variety of electronic devices, from phones and PCs to ECUs in cars and servers ins... » read more

Closing The Performance Gap Between DRAM And AI Processors


As the workhorse of semiconductor memory, DRAM holds a unique place in the industry thanks to its large storage capacity and ability to feed data and program code to the host processor quickly. Lately, this unsung hero of the circuit board has been taking a backseat to its logic counterparts, as a wave of high-performance FPGAs, CPUs, GPUs, TPUs and custom accelerator ASICs emerges to meet t... » read more

Gearing Up For Hybrid Bonding


Hybrid bonding is becoming the preferred approach to making heterogeneous integration work, as the semiconductor industry shifts its focus from 2D scaling to 3D scaling. By stacking chiplets vertically in direct wafer-to-wafer bonds, chipmakers can leapfrog attainable interconnection pitch from 35µm in copper micro-bumps to 10µm or less. That reduces signal delay to negligible levels and e... » read more

Memory And High-Speed Digital Design


As DRAM gets faster, timing constraints, jitter, and signal integrity become harder to control. The real challenge is to understand what can go wrong early in the design process, and that becomes more complex with each new version of memory and higher signal speeds. Stephen Slater, product manager for EDA products at Keysight, talks about how simulation can be applied to these issues, what to t... » read more

CXL: The Future Of Memory Interconnect?


Momentum for sharing memory resources between processor cores is growing inside of data centers, where the explosion in data is driving the need to be able to scale memory up and down in a way that roughly mirrors how processors are used today. A year after the CXL Consortium and JEDEC signed a memorandum of understanding (MOU) to formalize collaboration between the two organizations, suppor... » read more

Week In Review: Manufacturing, Test


Bosch completed its acquisition of TSI Semiconductors to expand its SiC chips business, reports Reuters. In April, Bosch announced plans to invest $1.5 billion in the Roseville, California, foundry to convert TSI’s manufacturing facilities into state-of-the-art processes, with the first SiC chips due out in 2026. Bosch CEO Stefan Hartung said the full expansion "depends on the support of the... » read more

Demonstrating The Capabilities Of Virtual Wafer Process Modeling And Virtual Metrology


A technical paper titled “Review of virtual wafer process modeling and metrology for advanced technology development” was published by researchers at Coventor Inc., Lam Research. Abstract: "Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the p... » read more

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