tag: IBM

Who’s In Control Now?
By Ed Sperling - 31 Jul, 2009 - Comments: 0

By Ed Sperling Power is shifting across the design industry in multiple ways and sometimes across multiple continents, driven by complexity and cost pressures and entirely new forms of competition. On one side of the equation, foundries are dictating more of what goes on up front in the design cycle. Design for manufacturing is a prerequisite at 45nm and below, and they’re the ones dictatin... » read more

Where The Jobs Are
By Ed Sperling - 19 Jun, 2009 - Comments: 0

The job market for design and verification engineers seems to be exploding. In the past week, listings have been flooding onto jobs boards for LinkedIn semiconductor design groups. The only trouble is engineers may have to move to get the jobs—sometimes halfway around the globe. There have been a bunch of job postings for semiconductor expertise in India, the United Kingdom, as well as pla... » read more

Pain Points At 22nm And Beyond
By Ed Sperling - 27 May, 2009 - Comments: 0

By Ed Sperling The roadmap for 22nm has a giant pothole in the middle of it. That hole is supposed to be filled by extreme ultraviolet lithography, or EUV. Instead it is being patched up using immersion lithography, which is about to cause some monumental headaches for design teams. The difference is comparable to a surgeon using a chainsaw instead of a scalpel. The cut isn’t nearly as ... » read more

Writing Software For Low-Power Systems
By Ed Sperling - 15 Apr, 2009 - Comments: 0

By Ed Sperling Almost any discussion of software in low power systems these days involves some sort of multicore approach. That is particularly true at 90nm and below. At 65nm, unless there is a very distinct purpose for a low-power single-core device, it probably is utilizing at least two cores, and at 45nm the numbers can continue to rise, depending upon how many functions the chip is being... » read more

Advanced Materials: Mapping A Path To Low-Power Devices
By Cheryl Ajluni - 15 Mar, 2009 - Comments: 1

By Cheryl Ajluni For many electronics devices, especially those utilized in mobile applications, achieving low power is the Holy Grail. Unfortunately this goal is one that is not easily attained. In accordance with Moore’s Law, transistor density is continuing to increase. With each scaling, transistors are being designed smaller and faster to realize increased chip performance. But the risi... » read more

Writing Application Software Directly To The Metal
By Ed Sperling - 13 Mar, 2009 - Comments: 0

By Ed Sperling How necessary is an operating system? That question would have been considered superfluous a decade ago, possibly even blasphemous and career-limiting. But it now is beginning to surface in low-power discussions, particularly in compute-intensive applications where performance and power are both critical. General-purpose operating systems constantly call on the processor fo... » read more

Another Brick In The Wall
By Ed Sperling - 19 Feb, 2009 - Comments: 0

The wall is in sight.   Moore’s Law has propelled the semiconductor industry at an amazing velocity since it was first introduced in 1965, and despite some minor changes from 18 months to two years, we have pretty much stayed on course. In the past, most people thought we would hit the wall at 1 micron, and they thought it would happen again at 32nm. The road map appears pretty solid dow... » read more

NoC Your SoCs Off
By Ed Sperling - 19 Feb, 2009 - Comments: 0

By Ed Sperling The network on a chip (NoC) approach is gaining ground as an essential part of a system on a chip (SoC), providing the same kind of time-to-market advantage that well-tested intellectual property blocks provide. This follows almost eight years of hype about NoCs potential with little to show for it. Times have changed and there appear to be two main drivers, one technological a... » read more

The Quest For Faster Data Throughput On A Chip
By Ed Sperling - 19 Feb, 2009 - Comments: 0

By Ed Sperling As with all network topologies, the general rule is the faster the better. Jack Browne, VP of sales and marketing at Sonics, said his customers are asking for higher-speed interconnects. “Right now we’re at 300MHz,” he said. “They want to more than double that in the very near future and eventually get to 1GHz.” Getting to that speed is no simple ... » read more

The Trouble With On-Chip Interfaces
By Ed Sperling - 17 Dec, 2008 - Comments: 0

By Ed Sperling The trouble with standards is that many of them arise out of need rather than through careful planning, and often unilaterally. The typical scenario in chip design is that a company has an issue to solve, so it comes up with a solution. When it gets what it believes is critical mass behind the standard, the company that developed the solution opens it up to the rest of the ind... » read more

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