tag: Jasper Design Automation

Executive Insight: Kathryn Kranen
By Ed Sperling - 17 Feb, 2014 - Comments: 0

Semiconductor Engineering sat down with Kathryn Kranen, president and CEO of Jasper Design Automation, to discuss what's changing in the semiconductor industry, why that's happening, and what to watch out for. The interview is part of an ongoing series of in-depth interviews with top executives from all segments of the industry. SE: What keeps you up at night? Kranen: Figuring out ways to... » read more

Power Reduction Through Sequential Optimization
By Ann Mutschler - 13 Feb, 2014 - Comments: 1

Dealing with power is a multifaceted challenge and is an equal-opportunity problem — everybody can contribute to the solution and at many levels of abstraction. At the architectural or system level, fundamental tradeoffs are done and the engineering team decides how much memory the system needs, what type of processor, what performance, area, power, among other things. Some people may use ... » read more

The Other Side Of Formal
By Joseph Hupcey III - 13 Feb, 2014 - Comments: 1

It’s natural to think of formal analysis as a ruthlessly effective bug hunter and verification tool. But as the following case study from Homayoon Akhiani, presented at the Jasper Users Group (JUG) meeting shows, customers are using this approach to increase their SoC’s performance in ways that are very visible to the end-user of the part. Such visible improvements — in this case, minimiz... » read more

The Road Ahead For 2014: Tools
By Brian Bailey - 30 Jan, 2014 - Comments: 0

In the third and final part of this predictions series we see the natural conclusion of market shifts that are driving changes in semiconductors, and which in turn drive the tools and IP needed to create those systems. To be expected, the changes fall into a few areas: New tools, techniques and changes required for smaller geometries; A migration to higher-levels of abstraction and the... » read more

The Next Big Threat: Power And Performance
By Ed Sperling - 17 Jan, 2014 - Comments: 3

In the shiny world of consumer electronics and powerful computers, taking a grinder to the outside of a package may sound more like safecracking than sophisticated electronic code hacking. The reality is there is more in common than most semiconductor companies would like to admit, and the starting point often is just as crude. To no small extent, systems on chip have become miniature safes.... » read more

The Road Ahead For 2014
By Brian Bailey - 16 Jan, 2014 - Comments: 1

Semiconductor Engineering asked several thought leaders in the industry about the market drivers that are affecting their product planning operations for 2014. While almost everyone sees mobile devices continuing to be the major driver during 2014, there are some emerging areas that may start to have a larger impact. This article takes a look at some of those and the impacts they could have on ... » read more

Verifying Security Aspects of SoC Designs with Jasper App
By Various Writers - 15 Jan, 2014 - Comments: 0

This paper presents Jasper technology and methodology to verify the robustness of secure data access and the absence of functional paths touching secure areas of a design. Recently, we have seen an increasing demand in industrial hardware design to verify security information. Complex system-on-chips, such as those for cell phones, game consoles, and servers contain secure information. And it i... » read more

New Challenges Emerge With FinFETs
By Ed Sperling - 05 Dec, 2013 - Comments: 0

Working at advanced process nodes is always tricky. There are new things to worry about and more rules to deal with initially, yet the promised benefit is improved performance, power and area, or cost. But at the next process node, and the one after that, there are so many variables coming into play that trying to make sense of the PPA equation is becoming much more difficult. Early reports ... » read more

Tech Talk: Security Risks In An SoC
By Ed Sperling - 02 Dec, 2013 - Comments: 1

Lawrence Loh, vice president of engineering at Jasper Design Automation, maps out the security threats in complex systems on chip. [youtube vid=5GBYOnCBfEE] » read more

User Case Study
By Joseph Hupcey III - 08 Nov, 2013 - Comments: 0

In prior articles I’ve written in general terms of about formally verifying the impact of adding low power control circuitry with Jasper’s Low Power Verification App. At the recent Jasper User’s Group meeting on Oct. 22, a real world case study of this app in action at STMicro’s R&D center in India was presented. Here are some highlights from this paper: DUT in question: an AR... » read more

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