tag: portable stimulus

System-Level Verification Tackles New Role
By Brian Bailey - 15 Jun, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss advances in system-level verification with Larry Melling, product management director for the system verification group of [getentity id="22032" e_name="Cadence"]; Larry Lapides, vice president of sales for [getentity id="22036" e_name="Imperas”] and Jean-Marie Brunet, director of marketing for the emulation division of [getentity id="22017" e_nam... » read more

System-Level Verification Tackles New Role
By Brian Bailey - 09 Jun, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss advances in system-level verification with Larry Melling, product management director for the system verification group of [getentity id="22032" e_name="Cadence"]; Larry Lapides, VP of sales for [getentity id="22036" e_name="Imperas”] and Jean-Marie Brunet, director of marketing for the emulation division of [getentity id="22017" e_name="Mentor Gr... » read more

Open Standards For Verification?
By Ann Mutschler - 01 Jun, 2016 - Comments: 0

The increasing use of verification data for analyzing and testing complex designs is raising the stakes for more standardized or interoperable database formats. While interoperability between databases in chip design is not a new idea, it has a renewed sense of urgency. It takes more time and money to verify increasingly complex chips, and more of that data needs to be used earlier in the fl... » read more

The Top Five Trends in Verification to Watch for at DAC 2016
By Frank Schirrmeister - 26 May, 2016 - Comments: 0

The Design Automation Conference in Austin is upon us, so it's time for my annual preview of what to look for. In my mind, five trends stand out and are clearly visible in the DAC program as well as in what we are presenting at our booth: Stronger ties between verification engines Software-driven verification with portable stimulus Metric-driven verification Application specificity ... » read more

Bridging the IP Divide
By Brian Bailey - 18 May, 2016 - Comments: 1

IP reuse enabled greater efficiency in the creation of large, complex SoCs, but even after 20 years there are few tools to bridge the divide between the IP provider and the IP user. The problem is that there is an implicit fuzzy contract describing how the IP should be used, what capabilities it provides, and the extent of the verification that has been performed. IP vendors have been trying to... » read more

Full Coverage Or Full Monty
By Brian Bailey - 22 Jun, 2015 - Comments: 0

Without adequate coverage metrics and tools, verification engineers would never be able to answer the proverbial question: are we done yet? But a lot has changed in the design flow since the existing set of metrics was defined. Does it still ensure that the right things get verified, that time is not wasted on things deemed unimportant or a duplication of effort, and can it handle today’s hie... » read more

Accellera Adds Portable Stimulus Group
By Brian Bailey - 11 Feb, 2015 - Comments: 0

[getentity id="22028" e_name="Accellera"] created a working group for the portable test and stimulus, which would allow engineering teams to create the test once and be able to run it throughout the flow. This is a big deal in verification because it allows horizontal reuse of a [getkc id="55" kc_name="testbench"]. Test patterns run on the processors in a design and that enables the test to ... » read more

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