tag: portable stimulus

Debugging Debug
By Brian Bailey - 22 Feb, 2018 - Comments: 2

There appears to be an unwritten law about the time spent in debug-it is a constant. It could be that all gains made by improvements in tools and methodologies are offset by increases in complexity, or that the debug process causes design teams to be more conservative. It could be that no matter how much time spent on debug, the only thing accomplished is to move bugs to places that are less... » read more

Verification Of Functional Safety (Part 2)
By Brian Bailey - 22 Feb, 2018 - Comments: 0

The automotive industry is grappling with a tradeoff between cost and safety. Safety is well understood in industries that are cost-insensitive, such as aerospace and medical, and the consumer industry has a long track record of driving down costs while increasing functionality. But can these two industries be brought together in a safe and effective manner to enable automobiles to achieve the ... » read more

DVCon Committee Picks
By Brian Bailey - 25 Jan, 2018 - Comments: 0

A typical development team contains more verification engineers than design engineers, and that skew is getting wider. You can expect the trend to increase given that verification teams are now getting loaded with added complexity from heterogeneous multi-core systems, functional safety, neural networks and security-in addition to increasing size. Companies that do not keep up with the lates... » read more

Raising SoC Development Productivity With Portable Stimulus
By Mark Olen - 25 Jan, 2018 - Comments: 0

The semiconductor industry has achieved significant productivity increases by virtue of the development, deployment, and scalability of reusable design IP. The EDA industry has also achieved significant productivity increases by virtue of the development, deployment, and scalability of reusable verification IP. A remaining bottleneck in the SoC development process stems from the inability to re... » read more

Predictions: Methodologies And Tools
By Brian Bailey - 25 Jan, 2018 - Comments: 0

Predictions are divided into four posts this year. Part one covered markets and drivers. The second part looked at manufacturing, devices and companies and this part will cover methodologies and tools. In addition, the outlook from EDA executives will be provided in a separate post. Intellectual property As designs get larger, it should be no surprise that the size of the [getkc id="43" kc_... » read more

Reflection On 2017: Design And EDA
By Brian Bailey - 03 Jan, 2018 - Comments: 0

People love to make predictions, and most of the time they have it easy, but at Semiconductor Engineering, we ask them to look back on the predictions they make each year and to assess how close to the mark they were. We see what they missed and what surprised them. Not everyone accepts our offer to grade themselves, but most have this year. (Part one looked at the predictions associated with s... » read more

Which Verification Engine?
By Ed Sperling - 02 Jan, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss the state of verification with Jean-Marie Brunet, senior director of marketing for emulation at [getentity id="22017" e_name="Mentor, a Siemens Business"]; Frank Schirrmeister, senior group director for product management at [getentity id="22032" e_name="Cadence"]; Dave Kelf, vice president of marketing at [getentity id="22395" e_name="OneSpin Solut... » read more

And The Winner Is…
By Brian Bailey - 21 Dec, 2017 - Comments: 0

Finding out what resonates with our readers is important, so each year I look back through the list of the best-read articles for the channels that I write for. While this simple strategy does favor articles published during the early part of the year, the fact that our readership continues to grow, partially offsets this bias. For example, in Low Power/High Performance (LPHP) a quarter of the ... » read more

The Trouble With Models
By Ed Sperling - 20 Dec, 2017 - Comments: 0

Models are becoming more difficult to develop, integrate and utilize effectively at 10/7nm and beyond as design complexity, process variation and physical effects add to the number of variables that need to be taken into account. Modeling is a way of abstracting the complexity in various parts of the semiconductor design, and there can be dozens of models required for complex SoCs. Some are ... » read more

Which Verification Engine? (Part 2)
By Ed Sperling - 06 Dec, 2017 - Comments: 1

Semiconductor Engineering sat down to discuss the state of verification with Jean-Marie Brunet, senior director of marketing for emulation at [getentity id="22017" e_name="Mentor, a Siemens Business"]; Frank Schirrmeister, senior group director for product management at [getentity id="22032" e_name="Cadence"]; Dave Kelf, vice president of marketing at [getentity id="22395" e_name="OneSpin Solut... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy