tag: Advantest

Using AI To Glue Disparate IC Ecosystem Data
By Ed Sperling and Ann Mutschler - 26 Sep, 2024 - Comments: 0

AI holds the potential to change how companies interact throughout the global semiconductor ecosystem, gluing together different data types and processes that can be shared between companies that in the past had little or no direct connections. Chipmakers always have used abstraction layers to see the bigger picture of how the various components of a chip go together, allowing them to pinpoi... » read more

Promises and Perils of Parallel Test
By Anne Meixner - 10 Sep, 2024 - Comments: 1

Testing multiple devices at the same time is not providing the equivalent reduction in overall test time due to a combination of test execution issues, the complexity of the devices being tested, and the complex tradeoffs required for parallelism. Parallel testing is now the norm — from full wafer probe DRAM testing with thousands of dies to two-site testing for complex, high-performance c... » read more

Standardizing Defect Coverage In Analog/Mixed Signal Test
By Gregory Haley - 10 Sep, 2024 - Comments: 0

A newly drafted IEEE standard will bring more consistency to defect metrics in analog/mixed (AMS) designs, a long-overdue step that has become too difficult to ignore in the costly heterogeneous assemblies being deployed inside of data centers and mobile devices. Standardizing analog is no simple feat due to the legacy approach to AMS design, and this is not the first attempt at improving te... » read more

From Mobile Phones To Robotics: How The Industry Continues To Drive Innovation
By Keith Schaub - 10 Sep, 2024 - Comments: 0

I recently had the opportunity to host Pierre Cambou, Principal Analyst for Global Semiconductors at Yole Group, on the Advantest podcast. What struck me about our conversation was while we focused on what was going on in the mobile market, the entire talk was reflective of the cyclical nature of the semiconductor industry and how technology can drive intense cycles of innovation. As Pierre ... » read more

Chip Industry Week In Review
By The SE Staff - 09 Aug, 2024 - Comments: 0

Three Fraunhofer Institutes (IIS/EAS, IZM, and ENAS) launched the Chiplet Center of Excellence, a research initiative to support the commercial introduction of chiplet technology. The center initially will focus on automotive electronics, developing workflows and methods for electronics design, demonstrator construction, and the evaluation of reliability. The UCIe Consortium published the Un... » read more

AI/ML’s Role In Design And Test Expands
By Laura Peters - 06 Aug, 2024 - Comments: 1

The role of AI and ML in test keeps growing, providing significant time and money savings that often exceed initial expectations. But it doesn't work in all cases, sometimes even disrupting well-tested process flows with questionable return on investment. One of the big attractions of AI is its ability to apply analytics to large data sets that are otherwise limited by human capabilities. In... » read more

Leveraging AI To Efficiently Test AI Chips
By Ira Leventhal - 06 Aug, 2024 - Comments: 0

In the fast-paced world of technology, where innovation and efficiency are paramount, integrating artificial intelligence (AI) and machine learning (ML) into the semiconductor testing ecosystem has become of critical importance due to ongoing challenges with accuracy and reliability. AI and ML algorithms are used to identify patterns and anomalies that might not be discovered by human testers o... » read more

Chip Industry Week in Review
By The SE Staff - 02 Aug, 2024 - Comments: 0

Okinawa Institute of Science and Technology proposed a new EUV litho technology using only four reflective mirrors and a new method of illumination optics that it claims will use 1/10 the power and cost half as much as existing EUV technology from ASML. Applied Materials may not receive expected U.S. funding to build a $4 billion research facility in Sunnyvale, CA, due to internal government... » read more

Chip Industry Week In Review
By The SE Staff - 12 Jul, 2024 - Comments: 0

The U.S. Department of Commerce issued a notice of intent  to fund new R&D activities to establish and accelerate domestic advanced packaging capacity. CHIPS for America expects to award up to $1.6 billion in funding innovation across five R&D areas, as outlined in the vision for the National Advanced Packaging Manufacturing Program (NAPMP), with about $150 million per award in each... » read more

Delivering On Power During HPC Test
By Anne Meixner - 09 Jul, 2024 - Comments: 0

The industry’s insatiable need for power in high-performance computing (HPC) is creating problems for test cells, which need to deliver very high currents at very consistent voltage levels through the power delivery network (PDN). In response, ATE, wafer probe, and contactor vendors are introducing some innovative approaches and test procedures that can ensure robust power delivery to ATE pro... » read more

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