Advanced Packaging Drives Test And Metrology Innovations


Advanced packaging has become a focal point for innovation as the semiconductor industry continues to push for increased transistor density and better performance. But the pace of change is accelerating, making it harder for the entire ecosystem to keep up with those changes. In the past, major developments were roughly on an 18-month to 2-year cadence. Today, this is happening every few mon... » read more

Yield Management Embraces Expanding Role


Competitive pressures, shrinking time-to-market windows, and increased customization are collectively changing the dynamics and demands for yield management systems, shifting left from the fab to the design flow and right to assembly, packaging, and in-field analysis. The basic role of yield management systems is still expediting new product introductions, reducing scrap, and delivering grea... » read more

Balancing Parallel Test Productivity With Yield & Cost


Parallel test is used for nearly every device produced by fabs and OSATs, but it can reduce yield and increase the cost of test boards and operations. This is a well-understood tradeoff for ensuring consistent test accuracy across multiple sites and reducing test time. Collectively, ATEs and multi-site test boards — DUT interface boards (DIBs), probe cards, and load boards — significantl... » read more

A Renaissance Of Innovation


Innovation in semiconductor testing plays a critical role in the advancement of the semiconductor industry, ensuring that the chips and components that power modern technology are reliable, efficient, and capable of meeting the ever-increasing demands of various applications. As semiconductors become more complex, the methods and technologies used to test them must also evolve to maintain quali... » read more

Chip Industry Week In Review


Siemens announced plans to acquire Altair Engineering, a provider of industrial simulation and analysis, data science, and high-performance computing (HPC) software, for about $10 billion. Altair's software will become part of Siemens' Xcelerator portfolio and provide a boost to physics-based digital twins. Onto Innovation bought Lumina Instruments, a San Jose, California-based maker of lase... » read more

ML Model Usage For Various Life Stages Of Semiconductor Test


By Shinji Hioki and Ken Butler From development through high volume manufacturing (HVM), semiconductor manufacturers’ pain points change based on the life stages. Each stage requires different types of applications to help with business needs. At the early stage, where the design and process are still immature, understanding the root causes of maverick material and implementing fixes is th... » read more

Signals In The Noise: Tackling High-Frequency IC Test


The need for high-frequency semiconductor devices is surging, fueled by growing demand for advanced telecommunications, faster sensors, and increasingly autonomous vehicles. The advent of millimeter-wave communication in 5G and 6G is pushing manufacturers to develop chips capable of handling frequencies that were once considered out of reach. However, while these technologies promise faster ... » read more

Chip Industry Week In Review


Imec announced a new automotive chiplet consortium to evaluate which different architectures and packaging technologies are best for automotive applications. Initial members includes Arm, ASE, Cadence, Siemens, Synopsys, Bosch, BMW, Tenstorrent, Valeo, and SiliconAuto. Imec also launched star, a global network bringing together automotive and semiconductor innovators to address technological c... » read more

Using AI To Glue Disparate IC Ecosystem Data


AI holds the potential to change how companies interact throughout the global semiconductor ecosystem, gluing together different data types and processes that can be shared between companies that in the past had little or no direct connections. Chipmakers always have used abstraction layers to see the bigger picture of how the various components of a chip go together, allowing them to pinpoi... » read more

Promises and Perils of Parallel Test


Testing multiple devices at the same time is not providing the equivalent reduction in overall test time due to a combination of test execution issues, the complexity of the devices being tested, and the complex tradeoffs required for parallelism. Parallel testing is now the norm — from full wafer probe DRAM testing with thousands of dies to two-site testing for complex, high-performance c... » read more

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