Quinn Jacobson, strategic architect at Achronix, talks about security in FPGAs, including how to prevent reverse engineering of IP, how to make sure the design is authentic, and how to limit access to IP in transit and in the chip.
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Fraunhofer's commercial chiplet push; UCIe 2.0; SK hynix HBM funding for Indiana; IC sales up 18% QoQ; high-NA EUV ready; Infineon's new SiC fab; Arm and Cadence partner with Malaysia.
Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.
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