Formal’s Roadmap

By Brian Bailey - 30 Nov, 2016 - Comments: 0

Formal verification has come a long way in the past five years as it focused on narrow tasks within the verification flow. Semiconductor Engineering sat down to discuss that progress, and the future of formal technologies, with [getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"]; Harry Foster, chief verification scientist at [g... » read more

Formal’s Roadmap

By Brian Bailey - 22 Nov, 2016 - Comments: 0

Gaps In The Verification Flow

By Brian Bailey - 01 Nov, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the state of the functional verification flow with Stephen Bailey, director of emerging companies at [getentity id="22017" e_name="Mentor Graphics"]; [getperson id="11079" comment="Anupam Bakshi"], CEO of [getentity id="22168" e_name="Agnisys"]; [getperson id="11124" comment="Mike Bartley"], CEO of [getentity id="22868" e_name="Test and Verification... » read more

Gaps In The Verification Flow

By Brian Bailey - 25 Oct, 2016 - Comments: 0

Gaps In The Verification Flow

By Brian Bailey - 29 Sep, 2016 - Comments: 0

Can Verification Meet In The Middle?

By Brian Bailey - 20 Jul, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss these issues with; Stan Sokorac, senior principal design engineer for [getentity id="22186" comment="ARM"]; Frank Schirrmeister, senior group director for product marketing for the system development suite of [getentity id="22032" e_name="Cadence"]; Harry Foster, chief verification scientist at [getentity id="22017" e_name="Mentor Graphics"], Bernie... » read more

Can Verification Meet In The Middle?

By Brian Bailey - 30 Jun, 2016 - Comments: 0

Since the dawn of time for the EDA industry, the classic V diagram has defined the primary design flow. On the left hand side of the V, the design is progressively refined and partitioned into smaller pieces. At the bottom of the V, verification takes over and as you travel up the right-hand side of the V, verification and integration happens until the entire design has been assembled and valid... » read more

Spec-Driven Design

By Ed Sperling - 10 Jun, 2016 - Comments: 0

Anupam Bakshi, CEO of Agnisys, sat down with Semiconductor Engineering to discuss problems in the design flow and what needs to be fixed. What follows are excerpts of that conversation. SE: What are the big problems facing the industry? Bakshi: There is a disconnect from the specification down to the implementation. That's why verification has become so big. Specification down to implemen... » read more

Open Standards For Verification?

By Ann Mutschler - 01 Jun, 2016 - Comments: 0

The increasing use of verification data for analyzing and testing complex designs is raising the stakes for more standardized or interoperable database formats. While interoperability between databases in chip design is not a new idea, it has a renewed sense of urgency. It takes more time and money to verify increasingly complex chips, and more of that data needs to be used earlier in the fl... » read more

The Week In Review: Design

By Jesse Allen - 27 May, 2016 - Comments: 0

Mergers & Acquisitions Synopsys made a couple of announcements this week related to its TCAD business. First, they acquired Gold Standard Simulations, which clearly became a major factor in the release of a pre-wafer simulation solution to help semiconductor manufacturers reduce process node development time. The new solution aims to provide a comprehensive process, transistor and circui... » read more

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tag: Agnisys

Formal’s Roadmap

Formal’s Roadmap

Gaps In The Verification Flow

Gaps In The Verification Flow

Gaps In The Verification Flow

Can Verification Meet In The Middle?

Can Verification Meet In The Middle?

Spec-Driven Design

Open Standards For Verification?

The Week In Review: Design