Who Benefits From Chiplets, And When


Experts at the Table: Semiconductor Engineering sat down to discuss new packaging approaches and integration issues with Anirudh Devgan, president and CEO of Cadence; Joseph Sawicki, executive vice president of Siemens EDA; Niels Faché, vice president and general manager at Keysight; Simon Segars, advisor at Arm; and Aki Fujimura, chairman and CEO of D2S. This discussion was held in front of a... » read more

Week In Review: Design, Low Power


EnSilica listed on the London Stock Exchange's AIM market under the ticker ENSI. EnSilica designs mixed signal ASICs for system developers in the automotive, industrial, healthcare, and communications markets. It also has a portfolio of core IP covering cryptography, radar and communications systems. AIM is the LSE’s market for small and medium sized growth companies. "In connection with Admi... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive, mobility Cadence is now an official technology partner of the McLaren Formula 1 Team. The team will use Cadence’s Fidelity CFD Software to look at the computational fluid dynamics (CFD) of the airflow around the race cars and predict how a car design will affect the airflow. Infineon uncorked its XENSIV 60 GHz automotive radar sensor for in-cabin monitoring systems. One use ca... » read more

How To Optimize A Processor


Optimizing any system is a multi-layered problem, but when it involves a processor there are at least three levels to consider. Architects must be capable of thinking across these boundaries because the role of each of the layers must be both understood and balanced. The first level of potential optimization is at the system level. For example, how does data come in and out of the processing... » read more

Repositioning For A Changing IC Market


Sailesh Chittipeddi, executive vice president at Renesas, sat down with Semiconductor Engineering to talk about how changes in end markets are shifting demand for technology. What follows are excerpts of that conversation. SE: Renesas has acquired a number of companies over the past several years. What's the goal? Chittipeddi: The goal very simply is to create an industry leading solutio... » read more

Standardizing Chiplet Interconnects


The chip industry is making progress on standardizing the infrastructure for chiplets, setting the stage for faster and more predictable integration of different functions and features from different vendors. The ability to choose from a menu of small, highly specialized chips, and to mix and match them for specific applications and use cases, has been on the horizon for more than a decade. ... » read more

Week In Review: Manufacturing, Test


GlobalFoundries launched GF Labs, an “open framework of internal and external research and development initiatives that deliver a differentiated pipeline of market-driven process technology solutions for future data-centric, connected, intelligent and secure applications.” Greg Bartlett, GF's senior vice president of technology, engineering at quality, said the goal is to develop and exp... » read more

Week In Review: Design, Low Power


Cadence's digital full flow was certified for the GlobalFoundries 12LP/12LP+ process platforms. The certified tools include the Innovus Implementation System, Genus Synthesis Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, Quantus Extraction Solution, Litho Physical Analyzer (LPA), and Pegasus Verification System. Siemens Digital Industries Software's Calibre nm... » read more

Week in Review: Manufacturing, Test


Industry Numbers NAND flash memory is forecast to hit US $83 billion this year, an increase of 24%. DRAM is projected to hit $118 billion, up 25%, according to a recent Yole report. Both are historic records. DRAM and NAND revenues are expected to be a $260 billion market in 2027 (combined), with advanced technologies such as EUV lithography, hybrid bonding and 3D DRAM driving this. SEMI in... » read more

Week In Review: Design, Low Power


Tools & IP MIPS announced its first products based on the RISC-V ISA. The eVocore IP cores are designed to provide a flexible foundation for heterogeneous compute, supporting combinations of eVocore processors as well as other accelerators, with a Coherence Manager that maintains L2 cache and system-level coherency between all cores, main memory, and I/O devices. They target high-performan... » read more

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