tag: ANSYS

Have Margins Outlived Their Usefulness?
By Aveek Sarkar - 20 Apr, 2016 - Comments: 0

To automate the process of solving complex design problems, the traditional approach has been to partition them into smaller, manageable tasks. For each task, we have built the best possible solution which we continuously refine over time. Additionally, we have managed the interdependencies between tasks by defining boundaries or margins; these often have been best- and worst-case values used t... » read more

Blog Review: April 20
By Jesse Allen - 20 Apr, 2016 - Comments: 0

Synopsys' Michael Posner digs into the relationships between USB Type-C, USB 3.1, Power Delivery and DisplayPort specifications. Cadence's Paul McLellan listens in on a discussion of the memory market's growth in China, and what's on the horizon. Mentor's Andy Macleod looks at the challenges that come with the increased car customization consumers are demanding. An energy-harvesting, t... » read more

Rightsizing Challenges Grow
By Ed Sperling - 20 Apr, 2016 - Comments: 0

Rightsizing chip architectures is getting much more complicated. There are more options to choose from, more potential bottlenecks, and many more choices about what process to use at what process node and for which markets and price points. Rightsizing is a way of targeting chips to specific application needs, supplying sufficient performance while minimizing power and cost. It has been a to... » read more

The Week In Review: Design/IoT
By Jesse Allen - 15 Apr, 2016 - Comments: 0

Mergers & Acquisitions Cadence acquired [getentity id="22444" comment="Rocketick"], an Israel-based company focused on multicore parallel simulation. Founded in 2008, their original rise and claim to fame was acceleration on GPUs, having received significant funding from Nvidia. The deal is expected to close in the second quarter of fiscal 2016, and terms were not disclosed. Tools &am... » read more

Analyzing The Integrity Of Power
By Ann Mutschler - 14 Apr, 2016 - Comments: 0

Power analysis is shifting much earlier in the chip design process, with power emerging as the top design constraint at advanced process nodes. As engineering teams pack more functionality and content into bigger and more complex chips, they are having to deal with more complex interactions that affect everything from power to its impact on signal integrity and long-term reliability. That, i... » read more

Blog Review: April 13
By Jesse Allen - 13 Apr, 2016 - Comments: 0

A Lam Research staff writer discusses the transformational effects of NAND flash memory and looks at the challenges of the next step: building 3D NAND structures. With the recent reports of people lining up to preorder the Model 3, Tesla may seem like the hottest electric vehicle company right now. But Mentor's Andrew Macleod argues it may actually be BYD Auto, a Chinese company that that so... » read more

The Week In Review: Design/IoT
By Jesse Allen - 08 Apr, 2016 - Comments: 0

Tools Cadence unveiled the latest updates to its Virtuoso platform, adding enhanced data handling for up to 20X improvement in loading waveform databases in excess of 1GB and a 50X improvement in versioning and loading set-up files into the environment in the Analog Design Environment. Updates to the Layout Suite offer up to 100X accelerated zoom, pan, drag and draw performance on large layo... » read more

Blog Review: April 6
By Jesse Allen - 06 Apr, 2016 - Comments: 0

A wall of underground ice is being built to contain contaminated water runoff from the Fukushima nuclear power plant and Swedish researchers want to make windowpanes out of wood, in this week's top tech picks from Ansys' Justin Nescott. Plus, if you're concerned about being spied on by aliens, there's a way the earth could hide. Mentor's Andrew Macleod digs into the problems of centralizing ... » read more

The Week In Review: Design/IoT
By Jesse Allen - 01 Apr, 2016 - Comments: 0

Tools Synopsys unveiled a new custom design solution targeting FinFET layout, introducing visually-assisted routing automation, a built-in design rule checking engine, templates to apply previous layout decisions to new designs, and IC Compiler integration. TSMC certified the new tool for 10nm and 7nm FinFET process technologies. It has also been adopted by STMicroelectronics, GSI Technology... » read more

Blog Review: March 30
By Jesse Allen - 30 Mar, 2016 - Comments: 0

Are we in a new wave of formal? Mentor's Joe Hupcey III highlights several things from DVCon that indicate formal is becoming a cornerstone of mainstream verification flows. Synopsys' Graham Etchells continues his search for more ways to bring greater efficiency to the FinFET layout process, and the downsides to custom routing solutions. Cadence's Paul McLellan takes a look at TSMC's rapi... » read more

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