Sidestepping Lithography In Chip Manufacturing

By Katherine Derbyshire - 23 May, 2024 - Comments: 0

Rising lithography costs, shrinking feature sizes, and the need for an alternative to copper are collectively spurring new interest in area-selective deposition. An extension of atomic layer deposition, ASD seeks to build circuit features from the bottom up, without relying on lithography. Lithography will remain a critical tool for the foreseeable future. But it has long been the most expen... » read more

Design of Selective Deposition Processes For Nanoscale Electronic Devices

By Technical Paper Link - 27 Jun, 2023 - Comments: 0

A technical paper titled “Quantified Uniformity and Selectivity of TiO2 Films in 45-nm Half Pitch Patterns Using Area-Selective Deposition Supercycles” was published by researchers at IMEC, North Carolina State University, and KU Leuven. Abstract: "Area-selective deposition (ASD) shows great promise for sub-10 nm manufacturing in nanoelectronics, but significant challenges remain in scali... » read more

Site-Specific Compositional Info from Periodic Nanostructures Obtained Using Rutherford Backscattering Spectrometry

By Technical Paper Link - 28 Oct, 2022 - Comments: 0

A new technical paper titled "Quantification of area-selective deposition on nanometer-scale patterns using Rutherford backscattering spectrometry" was published by researchers at IMEC and KU Leuven. "We present a site-specific elemental analysis of nano-scale patterns whereby the data acquisition is based on Rutherford backscattering spectrometry (RBS). The analysis builds on probing a larg... » read more

ASD process that was performed in situ on the etch chamber

By Technical Paper Link - 06 May, 2022 - Comments: 0

New research paper entitled "Plasma-based area selective deposition for extreme ultraviolet resist defectivity reduction and process window improvement" from TEL Technology Center, Americas and IBM Research. Abstract: "Extreme ultraviolet (EUV) lithography has overcome significant challenges to become an essential enabler to the logic scaling roadmap. However, it remains limited by stocha... » read more

Extending Copper Interconnects To 2nm

By Laura Peters - 17 Mar, 2022 - Comments: 0

Transistor scaling is reaching a tipping point at 3nm, where nanosheet FETs will likely replace finFETs to meet performance, power, area, and cost (PPAC) goals. A significant architectural change is similarly being evaluated for copper interconnects at 2nm, a move that would reconfigure the way power is delivered to transistors. This approach relies on so-called buried power rails (BPRs) and... » read more

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tag: area-selective deposition

Sidestepping Lithography In Chip Manufacturing

Design of Selective Deposition Processes For Nanoscale Electronic Devices

Site-Specific Compositional Info from Periodic Nanostructures Obtained Using Rutherford Backscattering Spectrometry

ASD process that was performed in situ on the etch chamber

Extending Copper Interconnects To 2nm