tag: ARM

Enabling Cheaper Design
By Brian Bailey - 13 Sep, 2018 - Comments: 1

While the EDA industry tends to focus on cutting edge designs, where design costs are a minor portion of the total cost of product, the electronics industry has a very long tail. The further along the tail you go, the more significant design costs become as a percent of total cost. Many of those designs are traditionally built using standard parts, such as microcontrollers, but as additional... » read more

Open Throttle On Automotive Innovation
By Brian Fuller - 13 Sep, 2018 - Comments: 0

Like a race car accelerating out of a turn, the autonomous and semi-autonomous vehicle market is expanding faster than a lot of people expected. IHS Markit, for example, reported earlier this year that more than 33 million autonomous vehicles will be sold globally in 2040. The growth rate, IHS Markit suggests, is going to be torrid since the first year of significant volume for autonomous vehic... » read more

Foveated Rendering
By Arm - 12 Sep, 2018 - Comments: 0

Virtual Reality (VR) is becoming increasingly popular due to its ability to immerse the user into an experience. Those experiences can vary from watching a movie in a simulated theatre, having a look at your personal pictures as though they were paintings in a museum or finding yourself in front row seats of a huge sporting event. These specific experiences don’t stress the device hardware to... » read more

Blog Review: Sept. 12
By Jesse Allen - 12 Sep, 2018 - Comments: 0

Cadence's Paul McLellan checks out the impact the Meltdown, Spectre, and Foreshadow vulnerabilities will have on future processor design with an overview of speculative execution and why it's important to current architectures. Mentor's Matthew Ballance suggests some ways to find existing information and descriptions that can be used to jump-start the creation of portable stimulus models. ... » read more

Intel Buys NetSpeed for NoC, Fabric IP
By Jeff Dorsch - 10 Sep, 2018 - Comments: 0

Intel acquired NetSpeed Systems, taking in network-on-a-chip and interconnect fabric intellectual property for designing, developing, and testing system-on-a-chip devices. The acquisition gives Intel a key missing ingredient in its plan to develop customized heterogeneous solutions for its customers. The company now has various memory pieces, interconnect bridges, programmable logic and ASIC... » read more

Finding Security Holes In Hardware
By Ed Sperling - 06 Sep, 2018 - Comments: 0

At least three major security holes in processors were identified by Google's Project Zero over the past year, with more expected to roll out in coming months. Now the question is what to do about them. Since the beginning of the PC era, two requirements for hardware were backward compatibility and improvements in performance with each new version of processors. No one wants to replace their... » read more

Cache Speculation Side-Channels
By Arm - 05 Sep, 2018 - Comments: 0

This whitepaper looks at the susceptibility of Arm implementations following research findings from security researchers, including Google and MIT, on new potential cache timing side-channels exploiting processor speculation. This paper also outlines possible mitigations that can be employed for software designed to run on existing Arm processors. To read more, click here. » read more

Blog Review: Sept. 5
By Jesse Allen - 05 Sep, 2018 - Comments: 0

Synopsys' Taylor Armerding looks at a case of exploding costs – up to $17 million – when the city of Atlanta, Georgia fell victim to the SamSam ransomware, plus the lessons other cities can take to improve their security. Cadence's Paul McLellan traces how a landmark moment in object recognition, the ImageNet database, has spurred increasingly better object recognition algorithms for alm... » read more

Using More Verification Cores
By Brian Bailey - 30 Aug, 2018 - Comments: 1

Semiconductor Engineering sat down to talk about parallelization efforts within EDA with Andrea Casotto, chief scientist for Altair; Adam Sherer, product management group director in the System & Verification Group of Cadence; Harry Foster, chief scientist for Mentor, a Siemens Business; Vladislav Palfy, global manager for applications engineering at OneSpin; Vigyan Singhal, chief Oski for ... » read more

Blog Review: Aug. 29
By Jesse Allen - 29 Aug, 2018 - Comments: 0

Mentor's Joe Hupcey III addresses inconclusive results in formal verification with tips on how to reduce the complexity of “assumption” properties to make them easier for the formal engines to digest and reach a solution. Cadence's Meera Collier looks beyond the immediate appeal of autonomous cars to the broader social implications of urban sprawl, public transit funding, and gentrificat... » read more

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