Using More Verification Cores


Semiconductor Engineering sat down to talk about parallelization efforts within EDA with Andrea Casotto, chief scientist for Altair; Adam Sherer, product management group director in the System & Verification Group of Cadence; Harry Foster, chief scientist for Mentor, a Siemens Business; Vladislav Palfy, global manager for applications engineering at OneSpin; Vigyan Singhal, chief Oski for ... » read more

Blog Review: Aug. 29


Mentor's Joe Hupcey III addresses inconclusive results in formal verification with tips on how to reduce the complexity of “assumption” properties to make them easier for the formal engines to digest and reach a solution. Cadence's Meera Collier looks beyond the immediate appeal of autonomous cars to the broader social implications of urban sprawl, public transit funding, and gentrificat... » read more

802.11ax: Faster Wireless


Marvell's Sathya Subramanian talks with Semiconductor Engineering about the new 802.11ax wireless standard, how it will work with 5G and existing networks, and how to set up an integrated solution to reduce bottlenecks in the home and in the enterprise. https://youtu.be/KZP59qw6j4Y » read more

Week In Review: Design, Low Power


Wafer company Soitec and European missile manufacturer MBDA joined together to buy the assets of Dolphin Integration. The IP and EDA tool provider, founded in 1985 in Grenoble, France, has been struggling, recently concluding insolvency proceedings and going into receivership. The new joint venture will absorb Dolphin's 155 employees and be owned 60% by Soitec, 40% by MBDA. The two companies co... » read more

Week in Review: IoT, Security, Auto


Internet of Things Arm uncorked its first forward-looking CPU roadmap and performance numbers for client computing. The company said it expects to deliver annual performance improvements of more than 15% per year through 2020. The targeted market includes 5G, always-on, always-connected devices. C3 IoT will work with Google Cloud to support artificial intelligence and Internet of Things dep... » read more

Gaps In Verification Metrics


As design complexity has exploded, the verification effort has likewise grown exponentially, with many different types of verification being applied to different classes of design. A recent panel discussion with leading chipmakers examined this topic in an effort to shed light on design health and quality, measuring the success of verification, knowing when verification is complete, being on... » read more

Big Changes For Mainstream Chip Architectures


Chipmakers are working on new architectures that significantly increase the amount of data that can be processed per watt and per clock cycle, setting the stage for one of the biggest shifts in chip architectures in decades. All of the major chipmakers and systems vendors are changing direction, setting off an architectural race that includes everything from how data is read and written in m... » read more

Blog Review: Aug. 22


Cadence's Paul McLellan considers how much further we need to go to make EUV work for 5nm, the problem of cost, and ASML's EUV roadmap. In a video, Mentor's Colin Walls explains optimizing data in embedded software with a simple example of two ways to put data in memory and how to decide which is best. Synopsys' Fred Bals provides a rundown of the different types of application security t... » read more

Week In Review: Design, Low Power


Intel disclosed a speculative execution side-channel attack method called L1 Terminal Fault (L1TF). Leslie Culbertson, Intel's executive vice president and general manager of Product Assurance and Security, writes: "This method affects select microprocessor products supporting Intel Software Guard Extensions (Intel SGX) and was first reported to us by researchers at KU Leuven University, Techni... » read more

Blog Review: Aug. 15


Cadence's Paul McLellan checks out what's driving the growth of China's semiconductor industry plus the state of fab construction, from a CAPSA presentation by SEMI's Lung Chu. Mentor's Joe Hupcey III has some tips for how to handle inconclusive results in formal verification, starting with how to identify where the analysis got stuck. Synopsys' Taylor Armerding listens in on a presentati... » read more

← Older posts Newer posts →