Is PPA Relevant Today?


The optimization of power, performance, and area (PPA) has been at the core of chip design since the dawn of EDA, but these metrics are becoming less valuable without the context of how and where these chips will be used. Unlike in the past, however, that context now comes from factors outside of hardware development. And while PPA still serves as a useful proxy for many parts of the hardwar... » read more

Higher Density, More Data Create New Bottlenecks In AI Chips


Data movement is becoming a bigger problem at advanced nodes and in advanced packaging due to denser circuitry, more physical effects that can affect the integrity of signals or the devices themselves, and a significant increase in data from AI and machine learning. Just shrinking features in a design is no longer sufficient, given the scaling mismatch between SRAM-based L1 cache and digital... » read more

Evolving Edge Computing And Harnessing Heterogeneity


In the Evolving Edge Computing white paper, we highlighted 3 challenges to enable the Intelligent Edge, they are: Enabling hardware heterogeneity Removing development friction Ensuring security at scale This blog post examines the first in that list, heterogeneity. It will cover the ways in which heterogeneity appears, its effect on systems and some ideas for resolving its inher... » read more

Blog Review: Sept. 11


Cadence's Neha Joshi introduces the IEEE 1801 standard, also known as UPF (Unified Power Format), which offers a uniform framework for defining power domains, power states, and power intent to ensure consistency across diverse tools and phases of the design process. Siemens' John McMillan warns that known good die may not behave the same in 3D-ICs as they do standalone and suggests that mult... » read more

Software-Defined Vehicles for Dummies


This latest Dummies Guide takes you through the captivating world of software-defined vehicles (SDVs), offering important insights into the technologies and systems that propel SDVs, and their impact on the future of transportation. This book covers the foundational understanding of SDVs and progressively delves into their various aspects, exploring the potential implications of this rapidly ev... » read more

Chip Industry Week In Review


Concerns mount on the use of American-manufactured semiconductors in Russian weapons, with Analog Devices, AMD, Intel and TI set to testify next week before the U.S. Senate Permanent Subcommittee on Investigations. Also, U.S. and other government agencies issued a joint advisory and more details about ongoing Russian military cyberattacks, espionage, and sabotage. The U.S. Commerce Departmen... » read more

Balancing Programmability And Performance In Cars


The rate of change in the automotive industry is accelerating with the shift toward software-defined vehicles and ongoing advancements in algorithms and chip architectures. The challenge now is to figure out the best way to prevent rapid obsolescence, improve safety, and keep the cost of these changes to a minimum. Today, updatable automotive hardware is typically achieved through FPGAs, but... » read more

Shaping The Future Of Automotive Safety With V2X


In recent years, the automotive industry has witnessed a technological evolution that promises to redefine road safety and driving experiences. At the heart of this advancement is V2X technology, which stands for "vehicle-to-everything." This innovation allows vehicles to communicate with each other and their surroundings, enhancing road safety and efficiency. Understanding these cutting-edge d... » read more

Blog Review: Sept. 4


Synopsys' Jyotika Athavale and Randy Fish sit down with Google's Rama Govindaraju and Microsoft's Robert S. Chappell to discuss silent data corruption and why a solution will require chip designers and manufacturers, software and hardware engineers, vendors, and anyone involved in computer data to collaborate and take the issue seriously. Siemens' Karen Chow and Joel Mercier explain the rela... » read more

Blog Review: Aug. 28


Synopsys' Jon Ames checks out how the Ultra Ethernet Consortium aims to revolutionize networking by optimizing Ethernet for the rapidly evolving AI and HPC workloads by addressing critical issues like tail latency that are encountered by machine learning algorithms in large compute clusters. Cadence's Kos Gitchev introduces the DDR5 Multiplexed Rank DIMM (MRDIMM), a memory module technology ... » read more

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