Week In Review: Design, Low Power

By Jesse Allen - 13 May, 2022 - Comments: 0

Tools & IP MIPS announced its first products based on the RISC-V ISA. The eVocore IP cores are designed to provide a flexible foundation for heterogeneous compute, supporting combinations of eVocore processors as well as other accelerators, with a Coherence Manager that maintains L2 cache and system-level coherency between all cores, main memory, and I/O devices. They target high-performan... » read more

The Challenge Of Optimizing Chip Architectures For Workloads

By Brian Bailey - 12 May, 2022 - Comments: 1

It isn't possible to optimize a workload running on a system just by looking at hardware or software separately. They need to be developed together and intricately intertwined, an engineering feat that also requires bridging two worlds with have a long history of operating independently. In the early days of computing, hardware and software were designed and built by completely separate team... » read more

Software-Defined Cars

By Ann Mutschler - 11 May, 2022 - Comments: 0

Automotive architectures are becoming increasingly software-driven, a shift that simplifies upgrades and makes it easier to add new features into vehicles. All of this is enabled by the increasing digitalization of automotive functions and features, shifting from mechanical to electrical design, and increasingly from analog to digital data. That enables OEMs to add or up-sell features years ... » read more

Week In Review: Auto, Security, Pervasive Computing

By Susan Rambo - 06 May, 2022 - Comments: 0

Automotive, mobility Stellantis is buying Share Now, a car sharing service owned by BMW and Mercedes-Benz. Through the acquisition, Stellantis will be adding 3.4 million car sharing customers, 10,000 vehicles, and 14 new European cities to its Free2move car sharing service, which currently has 2 million users, 2,500 vehicles, and has 7 “mobility hubs” in the U.S. and Europe. ShareNow was a... » read more

Week In Review: Design, Low Power

By Jesse Allen - 06 May, 2022 - Comments: 0

Rambus will acquire Hardent, a provider of design services and IP. Rambus said Hardent's silicon design, verification, compression, and Error Correction Code (ECC) expertise will provide key resources for the Rambus CXL Memory Interconnect Initiative. “Driven by the demands of advanced workloads like AI/ML and the move to disaggregated data center architectures, industry momentum for CXL-base... » read more

Optimizing NoC-Based Designs

By Paul Graykowski - 05 May, 2022 - Comments: 0

Semiconductor development is currently in a phase of rapid evolution driven by the combination of new technologies and methodologies. The technique of combining multiple functions into systems-on-chips (SoCs) is continuing to grow in complexity. Rapid advancement in new technologies for market segments like data centers, robotics, ADAS and artificial intelligence/machine learning (AI/ML) are re... » read more

Choosing Which Tasks To Optimize In Chips

By Brian Bailey - 28 Apr, 2022 - Comments: 0

The optimization of one or more tasks is an important aspect of every SoC created, but with so many options now on the table it is often unclear which is best. Just a few years ago, most people were happy to buy processors from the likes of Intel, AMD and Nvidia, and IP cores from Arm. Some even wanted the extensibility that came from IP cores like Tensilica and ARC. Then, in 2018, John Henn... » read more

The Challenges Of Incremental Verification

By Brian Bailey - 28 Apr, 2022 - Comments: 1

Verification consumes more time and resources than design, and yet little headway is being made to optimize it. The reasons are complex, and there are more questions than there are answers. For example, what is the minimum verification required to gain confidence in a design change? How can you minimize the cost of finding out that the change was bad, or that it had unintended consequences? ... » read more

Architecting Faster Computers

By Brian Bailey - 14 Apr, 2022 - Comments: 3

To create faster computers, the industry must take a major step back and re-examine choices that were made half a century ago. One of the most likely approaches involves dropping demands for determinism, and this is being attempted in several different forms. Since the establishment of the von Neumann architecture for computers, small, incremental improvements have been made to architectures... » read more

Week In Review: Design, Low Power

By Jesse Allen - 08 Apr, 2022 - Comments: 0

Synopsys and Juniper Networks are forming a new, separate company that will provide the industry with an open silicon photonics platform that will include integrated lasers, optical amplifiers, and a full suite of photonic components to form a complete solution that will be accessible through a Process Design Kit (PDK). The new company is being formed, in part, from the carve-out of integrated ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Arteris IP

Week In Review: Design, Low Power

The Challenge Of Optimizing Chip Architectures For Workloads

Software-Defined Cars

Week In Review: Auto, Security, Pervasive Computing

Week In Review: Design, Low Power

Optimizing NoC-Based Designs

Choosing Which Tasks To Optimize In Chips

The Challenges Of Incremental Verification

Architecting Faster Computers

Week In Review: Design, Low Power