The Week In Review: System-Level Design

By Ed Sperling - 03 Jan, 2014 - Comments: 0

The big buzz at this year’s CES is around wearable computing, according to Gartner, and the big drivers will be fitness and digital health. The firm believes wearable electronics will be peripherals to smartphones, which will provide connectivity to store and analyze biodata. Hewlett-Packard plans to cut 34,000 employees by the end of this year, or roughly 11% of its workforce, according t... » read more

Intel Vs. Everyone Else

By Ed Sperling - 08 Jul, 2013 - Comments: 0

A report from ABI Research is starting to gain some attention. For cynics, the question of why now seems perfectly reasonable, considering the report was released early last month and promptly fell well under the semiconductor industry’s radar. But cynicism aside, it’s still interesting to compare specs for chips using ARM’s Cortex-A15, A9 and Qualcomm’s ARM-based Krait. The bottom ... » read more

Foundry Models In Transition

By Jeff Chappell - 18 Apr, 2013 - Comments: 0

By Jeff Chappell There may have been a time when AMD founder Jerry Sanders famous quote: "real men (i.e., real companies) have their own fabs” rang true, but in today's business climate it seems quaint at best. Fabless or fab-lite business models are more popular than ever today, while some IDMs have turned back the clock, so to speak, looking to improve capacity utilization and revenues ... » read more

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Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

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Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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The Week In Review: System-Level Design

Intel Vs. Everyone Else

Foundry Models In Transition

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