tag: Atrenta

Executive Insight: Ajoy Bose
By Ed Sperling - 21 Jul, 2014 - Comments: 1

SE: What keeps you awake at night? Bose: What I worry about more than anything else is the need for us (at Atrenta) to show growth on an ongoing basis. A company’s challenges change with the lifecycle of that company. In the early days you worry about survival and trying to establish yourself in the industry. Fortunately, Atrenta is a bigger company today, so the nature of the concerns has c... » read more

Where Do We Stand With CDC?
By Ann Mutschler - 18 Jul, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss where the industry stands on clock domain crossing with Charlie Janac, CEO of Arteris; Shaker Sarwary, VP of Formal Verification Products at Atrenta; Pranav Ashar, CTO at Real Intent; and Namit Gupta, CAE, Verification Group at Synopsys. What follows are excerpts of that conversation. SE: What are the biggest use models for CDC verification today... » read more

Blog Review: July 16
By Ed Sperling - 16 Jul, 2014 - Comments: 0

Mentor’s Scott Salzwedel describes a conversation that could very well happen in the future and it raises an interesting idea. As medical electronics proliferate, will emergency medical teams need to include out systems engineers? Cadence’s Brian Fuller has a summer engineering project that resembles the Bridge Over the River Kwai. He should win an Oscar for this one. Ansys’ Bill ... » read more

After Moore’s Law: More With Less
By Brian Bailey - 10 Jul, 2014 - Comments: 6

In the decades when Moore’s Law went unquestioned, the industry was able to migrate to the next smaller node and receive access to more devices that could be used for increased functionality and additional integration. While less significant transistor-level power savings have been seen from the more recent nodes, as leakage currents have increased, the additional levels of integration have b... » read more

IP And FinFETs At Advanced Nodes
By Ed Sperling - 10 Jul, 2014 - Comments: 2

Semiconductor Engineering sat down to discuss IP and finFETs at advanced nodes with Bernard Murphy, CTO of Atrenta; Warren Savage, president and CEO of IPextreme; Aveek Sarkar, vice president of engineering and product support at Ansys-Apache; Randy Smith, vice president of marketing at Sonics. What follows are excerpts of that conversation. SE: As we push into the next nodes, we’ve got a ... » read more

Supporting LP In New Process Nodes
By Ann Mutschler - 10 Jul, 2014 - Comments: 0

Manufacturing process nodes and EDA tools are advancing all the time, but not always utilized at the same pace. And from a tools perspective, there are challenges to supporting low power in new process nodes while maintaining and improving the existing process nodes. One way design teams address this is by leveraging the most advanced software on the less-than-bleeding edge designs. To th... » read more

Constraints Ubiquity: Impact On Managing Design Closure?
By Mark Baker - 10 Jul, 2014 - Comments: 0

By Mark Baker and Ravindra Aneja Maintaining completeness, correctness and consistency of design constraints is a challenge that is pervasive in the design flow. Multiple transformations, or touch points (as illustrated in the diagram below), exist during the design implementation stages. Additionally, there are parallel stages involving IP development and handoff resulting in SoC integration ... » read more

Next Bonanza: Security Holes
By Ed Sperling - 07 Jul, 2014 - Comments: 0

Security threats—both real and potential—are beginning to reshape the semiconductor business. These threats are drawing venture capitalists back into the industry as they race for the next big opportunity. They are blurring the lines between software and hardware, as threats grow in complexity at every level of a device and its myriad and sometimes perpetual connections to the outside wo... » read more

Moore’s Law Tail No Longer Wagging The Dog
By Brian Bailey - 26 Jun, 2014 - Comments: 3

In a recent special report titled “Will 7nm and 5nm really happen?” Semiconductor Engineering outlined the progress being made for new production nodes and the progress being made to overcome the technological challenges that they contain. But who are the likely candidates for those new nodes and who is going to pay for their development, including the EDA tools that will be necessary to ut... » read more

Asynchronous Is Mostly Academic
By Ann Mutschler - 26 Jun, 2014 - Comments: 4

There are a number of interesting technologies to keep an eye on in term of how and when they could be adopted for use in SoC design today, some of which include gallium arsenide, GPGPUs, 3D ICs and asynchronous logic. Asynchronous logic promises a number of benefits in some specific application areas, and one that buoys to the surface for potential near-term use is in the area of security a... » read more

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