A graph placement methodology for fast chip design

Abstract "Chip floorplanning is the engineering task of designing the physical layout of a computer chip. Despite five decades of research1, chip floorplanning has defied automation, requiring months of intense effort by physical design engineers to produce manufacturable layouts. Here we present a deep reinforcement learning approach to chip floorplanning. In under six hours, our method autom... » read more

Week In Review: Auto, Security, Pervasive Computing

Synopsys has added nanoscale and macroscale illumination optics to its RSoft Photonic Device Tools version 2020.03. ARVR designers can use the RSoft-LightTools Bidirectional Scattering Distribution Function (BSDF) interface to make interpolated BSDF files for optimized nanoscale and macroscale optics, such as freeform optical prism projectors, eye tracking technologies, and optical planar waveg... » read more