The Perfect Risk


The development of semiconductors is an act of risk management. Very simply put, if you take on too much risk, it could lead to product failure or a missed market window, both of which can cost $M. For a company that only produces one or two products a year, that can spell total disaster. If you do not take on enough risk, you are probably not going to end up with a competitive product that ... » read more

Betting Big On Discontinuity


Wally Rhines, president and CEO of Mentor, a Siemens Business, sat down with Semiconductor Engineering to talk about the booming chip industry, what's driving it, how long it will last and what changes are ahead in EDA and chip architectures. What follows are excerpts of that conversation. SE: The EDA and semiconductor industries are doing well right now. What's driving that growth? Rhine... » read more

Market Trends For Large Volume Semi Products


Material and capacity shortages typically prompt changes in normal operating procedures, especially purchasing strategies. If the uncertainty regarding world trade policies and tariffs are added on top of the shortages, the impact results in unusual gyrations in industry sales data and possible misleading signals. Discretes, analog and opto are the three largest semiconductor product categories... » read more

The Big Blur


Chip companies, research houses, foundries—and more recently large systems companies—have been developing alternative technologies to continue scaling power and performance. It's still not obvious which of those will win, let alone survive, or what they will do to the economics of developing chips. For more than five decades, the biggest concern was scaling devices in order to save money... » read more

Electromagnetic Analysis and Signoff: Cost Savings


By Nikolas Provatas and Magdy Abadir We are often asked by SoC design teams about the benefits of an electromagnetic analysis and signoff methodology. Here is an overview of some of the big “cost savings”. Time to Market Savings Utilizing an EM crosstalk analysis and signoff methodology provides designers with an “insurance policy” against the risk of EM coupling in their SOC des... » read more

System-Level Test: Where Does It Fit?


Our second C-Brief discusses where system-level test (SLT) best fits into your semiconductor test workflow. With automated testing equipment (ATE), a traditional workflow may consist of: Wafer sort (WS) Burn-in after packaging (BI) Combination of structural testing (ST) and functional testing (FT). As demands on high-volume manufacturing shift in response to wider industry and com... » read more

The Security Penalty


It's not clear if Meltdown, Spectre and Foreshadow caused actual security breaches, but they did prompt big processor vendors like Intel, Arm, AMD and IBM to fix these vulnerabilities before they were made public by Google's Project Zero. While all of this may make data center managers and consumers feel better in one respect, it has created a level of panic of a different sort. For decades,... » read more

Intel Buys NetSpeed for NoC, Fabric IP


Intel acquired NetSpeed Systems, taking in network-on-a-chip and interconnect fabric intellectual property for designing, developing, and testing system-on-a-chip devices. The acquisition gives Intel a key missing ingredient in its plan to develop customized heterogeneous solutions for its customers. The company now has various memory pieces, interconnect bridges, programmable logic and ASIC... » read more

Hiring And Firing


I doubt if there is a manager, in any company, who likes to fire people. In addition, most companies are very cautious about getting rid of people. Human resources departments often put in place lengthy and complex procedures to provide a clear and well-documented path to someone's termination. During a recent Oski executive dinner, participants were quite heated in their discussion about th... » read more

Solving Systemic Complexity


EDA and IP companies have begun branching out in entirely new directions over the past 12 to 18 months, pouring resources into entirely different problems than electrostatic issues and routing complexity. While they're still focused on solving complexity at 10/7/5nm, they also recognize that enabling Moore's Law isn't the only opportunity. For an increasing number of new and established chip... » read more

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