中文 English

PLANAR: A Programmable Accelerator For Near-Memory Data Rearrangement


Many applications employ irregular and sparse memory accesses that cannot take advantage of existing cache hierarchies in high performance processors. To solve this problem, Data Layout Transformation (DLT) techniques rearrange sparse data into a dense representation, improving locality and cache utilization. However, prior proposals in this space fail to provide a design that (i) scales with m... » read more

Power/Performance Bits: July 18


Ad hoc "cache hierarchies" Researchers at MIT and Carnegie Mellon University designed a system that reallocates cache access on the fly, to create new "cache hierarchies" tailored to the needs of particular programs. Dubbed Jenga, the system distinguishes between the physical locations of the separate memory banks that make up the shared cache. For each core, Jenga knows how long it would t... » read more