tag: Cadence Design Systems

Low Power Still Leads, But Energy Emerges As Future Focus
By Ann Mutschler - 10 Dec, 2020 - Comments: 1

In 2021 and beyond, chips used in smartphones, digital appliances, and nearly all major applications will need to go on a diet. As the amount of data being generated continues to swell, more processors are being added everywhere to sift through that data to determine what's useful, what isn't, and how to distribute it. All of that uses power, and not all of it is being done as efficiently as... » read more

Waking And Sleeping Create Current Transients
By Bryon Moyer - 10 Dec, 2020 - Comments: 0

Silicon power-saving techniques are helping to reduce the power required by data centers and other high-intensity computing environments, but they’ve also added a significant challenge for design teams. As islands on high-powered chips go to sleep and wake up, the current requirements change quickly. This happens in a few microseconds, at most. The rapid change of loading creates a challen... » read more

How To Speed Up Large-Scale EM Simulation Of ICs Without Compromising Accuracy
By Cadence - 09 Dec, 2020 - Comments: 0

With growing on-chip radio frequency (RF) content, electromagnetic (EM) simulation of the passives is critical for a variety of reasons — from selecting the right RF design candidates to detecting parasitic coupling that directly impacts performance. Being on-chip, accurate EM analysis requires a tie into the process technology in the form of process design kits (PDKs) as well as a foundry-ce... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 04 Dec, 2020 - Comments: 0

Security The United States Department of Defense added China's SMIC to its blacklist for its alleged cooperation with the Chinese military, reports Reuters. U.S. investors are asked not to invest in SMIC, among 35 other companies based in China on the list. Intel Labs launched the Private AI Collaborative Research Institute with Avast and Borsetta, to advance and develop technologies in pri... » read more

System Simulation For RF Link Budget Analysis
By Cadence - 02 Dec, 2020 - Comments: 0

This white paper examines how a more rigorous link budget analysis of an entire system can be determined through simulation, and how performing link budget analysis enables designers to address losses, gains, and power levels to meet the operational requirements of the radio communications system. Click here to read more. » read more

The Next Big Leap: Energy Optimization
By Brian Bailey - 16 Nov, 2020 - Comments: 1

The relationship between power and energy is technically simple, but its implication on the EDA flow is enormous. There are no tools or flows today that allow you to analyze, implement, and optimize a design for energy consumption, and getting to that point will require a paradigm shift within the semiconductor industry. The industry talks a lot about power, and power may have become a more ... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 13 Nov, 2020 - Comments: 0

Automotive Cadence achieved ASIL Level B in support of D (ASIL B(D))-compliant certification for its Tensilica ConnX B10 and ConnX B20 DSPs, which are designed for automotive radar, lidar, and vehicle-to-everything (V2X). SGS-TÜV Saar certified that the DSPs have support for random hardware faults and systematic faults. Synopsys is acquiring Moortec, whose process, voltage, and temperature... » read more

Designs Beyond The Reticle Limit
By Brian Bailey - 12 Nov, 2020 - Comments: 0

Designs continue to grow in size and complexity, but today they are reaching both physical and economic challenges. These challenges are causing a reversal of the integration trend that has provided much of the performance and power gains over the past couple of decades. The industry, far from giving up, is exploring new ways to enable designs to go beyond the reticle size, which is around 8... » read more

Dealing With Sub-Threshold Variation
By Bryon Moyer - 12 Nov, 2020 - Comments: 0

Chipmakers are pushing into sub-threshold operation in an effort to prolong battery life and reduce energy costs, adding a whole new set of challenges for design teams. While process and environmental variation long have been concerns for advanced silicon process nodes, most designs operate in the standard “super-threshold” regime. Sub-threshold designs, in contrast, have unique variatio... » read more

Difficult Memory Choices In AI Systems
By Ann Mutschler - 12 Nov, 2020 - Comments: 0

The number of memory choices and architectures is exploding, driven by the rapid evolution in AI and machine learning chips being designed for a wide range of very different end markets and systems. Models for some of these systems can range in size from 10 billion to 100 billion parameters, and they can vary greatly from one chip or application to the next. Neural network training and infer... » read more

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