IoT Creates New IP Requirements


With the rise of smart cities, cars and houses, an enhanced connectivity infrastructure bolstered by an increasingly connected culture, the Internet of Things (IoT) represents an exciting opportunity for semiconductor industry players. As such, market researchers at IDC expect the installed base of the Internet of Things will be approximately 212 billion "things" globally by the end of 2020 ... » read more

Design Guidelines For Embedded Real Time Face Detection Application


This paper presents steps for real-time deployment of face detection application on a programmable vector processor. The steps taken are general purpose in the sense that they can be used to implement similar computer vision algorithms on any mobile device. To download this white paper, click here. » read more

The Week In Review: Design


Tools Cadence rolled out a new verification planning and management tool that is based on SQL, which greatly improves functionality and performance and offers multi-user, multi-engine and multi-analysis capabilities. Database technology—in this case, Structured Query Language—remains one of the very few software platforms that can harness multiple processors effectively. Synopsys unveil... » read more

Abstractions: The Good, Bad And Ugly


Raising the level of abstraction has become almost a mantra among chipmakers and tools developers. By moving the vantage point up a couple rungs on the ladder, it’s easier to see how the individual parts of a design go together, to identify problems in the design as well as fixes to problems, and it all can happen much more quickly. That’s the theory, at least. And in most cases, it’s ... » read more

Are Processors Running Out Of Steam?


Check out any smart phone these days and you’ll find some reference to the number of cores in the device. It’s not the number of cores that makes a difference, though—or even the clock speed at which they run. Performance depends on the underlying design for how they’re utilized, how often that happens, how much memory they share, how much interaction there is between the cores, and the... » read more

The Week In Review: Design


Synopsys inked a deal to acquire Coverity, a San Francisco-based security startup that builds tools to test source code for defects and security risks, for $375 million. The purchase price is $350 million plus another $25 million in debt. The deal is expected to close in Synopsys’ fiscal Q2. The company announced its financial results for fiscal Q1 ended Jan. 31, as well. Revenue was $479.0 m... » read more

Designing An Efficient Multi-Core LTE-A Modem


LTE-Advanced represents the next generation mobile broadband, and in turn throws the challenge to the designers to create highly power efficient mobile devices capable of delivering these services. ARM, the leading supplier of embedded processors, physical IP and inter-connect fabric, along with CEVA propose a joint analysis looking at the design considerations that are required to realize the ... » read more

Week In Review: System-Level Design


Cadence agreed to buy Forte Design Systems for an undisclosed sum, adding further proof that the market for high-level synthesis and tools that run at higher levels of abstraction is finally hitting its stride. Behind this acquisition is a rising pain level due to increasing complexity in SoCs—IP integration, low power concerns and much more of everything, from transistors to memories—has f... » read more

The Week In Review: System-Level Design


ARM and its ecosystem teamed up to create a server platform standard based on the ARMv8-A processor. The new Server Base System Architecture specification leverages a broad swath of companies in ARM’s ecosystem, including Microsoft, Red Hat, SUSE, Linaro, Citrix, AMD, Broadcom, Citrix and Cavium, as well as OEMs HP and Dell. ARM has been successful in leveraging an ecosystem to win the lion�... » read more

The Week in Review: System-Level Design


Cadence unveiled its next-gen power signoff tool, this one based upon parallel execution across multiple processors. The result is 10x speed improvement, according to the company. The signoff solution already is certified for TSMC’s 16nm finFET process for IR drop analysis and EM rule compliance, two of the big concerns with finFETs. Synopsys teamed up with CEVA to improve PPA for CEVA’s... » read more

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