Defect Analysis and Testing Framework For FOWLP Interconnects


A new technical paper titled "Defect Analysis and Built-In-Self-Test for Chiplet Interconnects in Fan-out Wafer-Level Packaging" was published by researchers at Arizona State University. Abstract "Fan-out wafer-level packaging (FOWLP) addresses the demand for higher interconnect densities by offering reduced form factor, improved signal integrity, and enhanced performance. However, FOWLP fa... » read more

Will AI Take My Job?


Everyone is talking about ChatGPT these days, and I am sure we will be comparing it with Google's new offering before long. I thought it was time that I gave it a quick spin, and since I am preparing to moderate a webinar about chiplets as I write this, I decided it was a good example of a fairly new field and would be a good test. I started by asking, "What are semiconductor chiplets, what ... » read more