Pathfinding Method That Models ECC Overhead for Chiplet Interconnects (UCLA)


A new technical paper, "Link Quality Aware Pathfinding for Chiplet Interconnects," was published by researchers at UCLA. Abstract "As chiplet-based integration advances, designers must select among short-reach die-to-die interconnect technologies with widely varying shoreline and areal bandwidth density, energy per bit, reach, and raw bit error rate (BER). Meeting stringent delivered BER ... » read more

Chiplet Fundamentals For Engineers: eBook


Multi-die assemblies are the next phase of Moore's Law, scaling up and out  to improve performance and add flexibility into designs. By decomposing SoCs into building blocks, yield improves for the individual dies and overall performance increases because a chip is no longer bound by reticle limits. But this is much harder than it sounds. Chiplets don't just snap together like LEGOs, and so... » read more

Inter-Chiplet Interconnect Topologies On Organic And Glass Substrates


A new technical paper titled "FoldedHexaTorus: An Inter-Chiplet Interconnect Topology for Chiplet-based Systems using Organic and Glass Substrates" was published by researchers at ETH Zurich. Abstract "Chiplet-based systems are rapidly gaining traction in the market. Two packaging options for such systems are the established organic substrates and the emerging glass substrates. These substr... » read more

Defect Analysis and Testing Framework For FOWLP Interconnects


A new technical paper titled "Defect Analysis and Built-In-Self-Test for Chiplet Interconnects in Fan-out Wafer-Level Packaging" was published by researchers at Arizona State University. Abstract "Fan-out wafer-level packaging (FOWLP) addresses the demand for higher interconnect densities by offering reduced form factor, improved signal integrity, and enhanced performance. However, FOWLP fa... » read more

Will AI Take My Job?


Everyone is talking about ChatGPT these days, and I am sure we will be comparing it with Google's new offering before long. I thought it was time that I gave it a quick spin, and since I am preparing to moderate a webinar about chiplets as I write this, I decided it was a good example of a fairly new field and would be a good test. I started by asking, "What are semiconductor chiplets, what ... » read more