Chip Industry Needs More Trust, Not Zero Trust

By Susan Rambo - 13 Jul, 2023 - Comments: 0

CISOs from Intel, TSMC, ASML, Applied Materials, and Lam Research unanimously called for the semiconductor industry to pull together to share information and develop cybersecurity protocols as a community at the Securing the Future for Semiconductor Manufacturing forum at SEMICON West. Chief information security officers (CISO) detailed their company’s method for dealing with cybersecurity... » read more

CISO’s Guide To Sensitive Data Protection

By Synopsys - 31 Mar, 2021 - Comments: 0

Emerging data protection and privacy laws are causing organizations to scramble to implement strategies that address regulatory compliance and data security governance. And the SolarWinds software supply chain attack, in which attackers inserted a malicious back door into its network software release that later led to sensitive data exposure, further underscores the need to secure the DevSecOps... » read more

CISO Research Identifies 4 Distinct Approaches To The Role

By Synopsys - 31 Jan, 2018 - Comments: 0

Every chief information security officer (CISO) is unique. They each have varying modes of operation that are influenced by long and distinguished careers. To understand CISO strategies and approaches, we decided to conduct a study. We gathered data in a series of extended in-person interviews with 25 CISOs with the goal of describing how a CISO’s work is organized and executed. To read mo... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: CISO

Chip Industry Needs More Trust, Not Zero Trust

CISO’s Guide To Sensitive Data Protection

CISO Research Identifies 4 Distinct Approaches To The Role