Addressing Today’s Complex Clock Modeling Issues With Veloce Emulation Technology

Earlier designs were smaller, less complex, and had simpler clocking. A few years back, verification was much easier and clock modeling was not such a big concern. With the drastic increase in the use of System-on-Chip (SoC), designs today are becoming extremely complex with an increasing number of peripherals/external interfaces to consider, requiring a higher numbers of asynchronous clocks. ... » read more