Designing A Better Clock Network

Laying the proper clock network architecture foundation makes all the difference for the best performance, power, and timing of a chip, particularly in advanced node SoCs packed with billions of transistors. Each transistor, which acts like a standard cell, needs a clock. An efficient clock network should ensure the switching transistors save power. In today’s advanced nodes, when a design... » read more

Enabling Big Chip AI Solutions Through Intelligent Clock Networks

Data centers, autonomous vehicles, and computer vision applications are pushing the limits of scalable AI compute. Data center chips face multi-trillion parameter models that continue growing every year. ADAS systems require flexibility and processing power for new model types, such as vision transformers. Edge AI solutions demand tight power budgets and the ability to process multiple models i... » read more

Clocks Getting Skewed Up

At a logical level, synchronous designs are very simple and the clock just happens. But the clocking network is possibly the most complex in a chip, and it's fraught with the most problems at the physical level. To some, the clock is the AC power supply of the chip. To others, it is an analog network almost beyond analysis. Ironically, there are no languages to describe clocking, few tools t... » read more