tag: code coverage

Comparing Formal And Simulation Code Coverage
By Siemens EDA - 09 Mar, 2022 - Comments: 0

There is a difference in semantics between code coverage generated from a simulator engine and code coverage generated from a formal engine. This paper seeks to raise the awareness of verification engineers on how best to make use of the code coverage data generated by different verification engines. The paper lays out the reasons for using code coverage and describes how simulation code covera... » read more

Seeing Is Believing: Visualizing Full Coverage Closure In Low-Power Designs
By Madhur Bhargava - 10 Oct, 2019 - Comments: 0

By Madhur Bhargava and Durgesh Prasad Lowering the power consumption and leakage in SoCs and other electrical designs has become a paramount concern in recent years. The reasons for this are many and well understood. The structures and techniques we use to accomplish this have made verification of so called low-power designs more complex and difficult than it is for designs where power usage... » read more

Utilizing More Data To Improve Chip Design
By Ann Mutschler - 28 Mar, 2019 - Comments: 0

Just about every step of the IC tool flow generates some amount of data. But certain steps generate a mind-boggling amount of data, not all of which is of equal value. The challenge is figuring out what's important for which parts of the design flow. That determines what to extract and loop back to engineers, and when that needs to be done in order to improve the reliability of increasingly com... » read more

Formal Signoff
By Ed Sperling - 04 Dec, 2018 - Comments: 0

Xiaolin Chen, senior AE at Synopsys, looks at what’s good enough coverage, what makes one assertion better than another, and where the potential holes are in verification. https://youtu.be/nBtKE0gDHBU » read more

Tech Talk: Better Coverage
By Ed Sperling - 08 Apr, 2015 - Comments: 1

Atrenta's Yuan Lu talks about code coverage, functional coverage and the use of assertions in debugging designs. [youtube vid=Hpm-l1z8HTo] » read more

Measuring Verification Accuracy
By Ann Mutschler - 20 Nov, 2014 - Comments: 0

[getkc id="10" kc_name="Verification"] is the unbounded challenge that continues to confound engineering teams across the globe, who want to know when "enough" is "good enough" to proceed to tapeout. The answer is not straightforward, and it includes more variables than in the past, particularly around power. Harry Foster, chief verification scientist at [getentity id="22017" e_name="Mentor ... » read more

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