tag: Compiler

HW-Native, GPU Compiler for Large-scale ML Production Systems (UC San Diego, Meta)
By Technical Paper Link - 18 May, 2026 - Comments: 0

A new technical paper, "TLX: Hardware-Native, Evolvable MIMW GPU Compiler for Large-scale Production Environments," was published by researchers at UC San Diego and Meta. Abstract "Modern GPUs increasingly rely on specialized hardware units and asynchronous coordination mechanisms, so performance depends on orchestrating data movement, tensor-core computation, and synchronization rather t... » read more

Accelerating Automotive Innovation: SRAM Compiler Breakthroughs for 5nm and 3nm SoCs
By Synopsys - 01 Apr, 2026 - Comments: 0

Modern automotive SoCs must deliver extreme performance, functional safety, and long‑term reliability — all under growing power and thermal constraints. This white paper explains how next‑generation Synopsys SRAM Compiler IP for TSMC N5A and N3A helps design teams meet these challenges with measurable gains in PPA, reliability, and system robustness. Why Read this White Paper: See... » read more

Overflowing Zoo: The Power Of Compilers
By Steve Roddy - 16 Oct, 2025 - Comments: 0

The term “model zoo” first gained prominence in the world of Artificial Intelligence/Machine Learning (AI/ML) beginning in the 2016-2017 timeframe. Originally used to describe open-source public repositories of working AI models — the most prominent of which today is Hugging Face — the term has since been adopted by nearly all vendors of AI chips and licensable Neural Processors Units (... » read more

LLM-Based Chiplet Design Generation Framework (Univ. of Minnesota)
By Technical Paper Link - 29 Aug, 2025 - Comments: 0

A new technical paper titled "MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debugging" was published by researchers at the University of Minnesota - Twin Cities. Abstract "As program workloads (e.g., AI) increase in size and algorithmic complexity, the primary challenge lies in their high dimensionality, encompassing computing cores, array sizes, and memory hierarch... » read more

Re-Targetable LLVM C/C++ Compiler For RISC-V
By Zdeněk Přikryl - 27 Jul, 2023 - Comments: 0

RISC-V is a modular instruction set architecture (ISA) with great customization capabilities that enable innovation and differentiation without fragmentation. On top of the baseline modules from ratified/standard ISA extensions, such as integer instructions or floating-point instructions, designers can add custom instructions: pure design freedom! And the reasons for adding instructions are man... » read more

Security-Aware Compiler-Assisted Countermeasure to Mitigate Fault Attacks on RISC-V
By Technical Paper Link - 26 Feb, 2023 - Comments: 0

A new technical paper titled "CompaSeC: A Compiler-Assisted Security Countermeasure to Address Instruction Skip Fault Attacks on RISC-V" was published by researchers at TU Munich and Fraunhofer Institute for Applied and Integrated Security (AISEC). Abstract "Fault-injection attacks are a risk for any computing system executing security-relevant tasks, such as a secure boot process. While ha... » read more

Optimizing Hardware Capacity, Utilizing Automatic Differentiation to Efficiently Compute Derivatives in Parallel Programming Models
By Technical Paper Link - 30 Nov, 2022 - Comments: 0

A technical paper titled "Scalable Automatic Differentiation of Multiple Parallel Paradigms through Compiler Augmentation" was published by researchers at MIT (CSAIL), Argonne National Lab, and TU Munich. The paper was a Best Paper Finalist and a Best Student Paper winner at SuperComputing 2022. Find the technical paper here. Published November 2022. The work "demonstrates how Enzyme opti... » read more

Custom Compiler Technology Highlights from 2022.06 Release
By Synopsys - 27 Jul, 2022 - Comments: 0

Weikai Sun, VP of Engineering at Synopsys, highlights the key technologies in Custom Compiler’s latest release. He shows how Synopsys’ innovative solutions for design closure, layout automation and emerging applications are increasing the productivity of design teams. Click here to access the  video white paper. » read more

Impact Of Instruction Memory On Processor PPA
By Roddy Urquhart - 24 Nov, 2020 - Comments: 0

The area of any part of a design contributes both to the silicon cost and to the power consumption. A simplistic following of the “A” in a processor IP vendor’s PPA numbers can be misleading. A processor is never in isolation but is part of a subsystem additionally including instruction memory, data memory, and peripherals. In most cases, instruction memory will be dominant and the proc... » read more

Fusion Compiler: Comprehensive RTL-to-GDSII Implementation System
By Synopsys - 07 Nov, 2018 - Comments: 0

The semiconductor industry is going through a renaissance period with waves of technological advancements and innovation. There has been a significant uptick in demand for silicon in recent years, driven by market sectors including automotive, artificial intelligence, cloud computing, and internet of things (IoT) that have their own unique mix of design and implementation requirements. The mobi... » read more

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