ML-based Routing Congestion And Delay Estimation In Vivado ML Edition

The FPGA physical design flow offers a compelling opportunity for Machine Learning for CAD (MLCAD) for the following reasons: • An ML solution can be applied wholesale to a device family. • There is a vast data farm that can be harvested from device models and design data from broad applications. • There is a single streamlined design flow that an be instrumented, annotated, and quer... » read more

How To Reduce Timing Closure Headaches

As chips have become more complex, timing closure has provided some of the most vexing challenges facing design engineers today. This step requires an increasing amount of time to complete and adds significantly to design costs and back-end schedule risks. Wire delay dominates transistor switching delay Building high-performance modern CPUs involves pipelining to achieve high frequencies. I... » read more

Routing Congestion Returns

By Ed Sperling Routing congestion has returned with a vengeance to SoC design, fueled by the advent of more third-party IP, more memory, a variety of new features, as well as the inability to scale wires at the same rate as transistors. This is certainly not a foreign concept for IC design. The markets for place and route tools were driven largely by the need to automate this kind of operat... » read more