Innovate By Customized Instructions, But Without Fragmenting The Ecosystem


This white paper reviews the design considerations for SoC designers when they deploy their hardware accelerators, and how software developers access the accelerators implemented using Arm Custom Instructions. Click here to read more. » read more

Domain-Specific Processors Enable More Than Moore


Last month was the 55th anniversary of Gordon Moore’s famous paper Cramming more components onto integrated circuits. He took a long-term view of the trends in integrated circuits being implemented using successively smaller feature sizes in silicon. Since that paper, integrated circuit developers have been relying on three of his predictions: The number of transistors per chip increas... » read more

Extending RISC-V ISA With Custom Instruction Set Extension


RISC-V ISA (Instruction Set Architecture) is designed in a modular way. It means that the ISA has several groups of instructions (ISA extensions) that can be enabled or disabled as needed. This allows implementing precisely the instruction groups that the application needs, without having to pay for area or power that will not be used. One of the groups is special; it has no predefined instruct... » read more