Wednesday At DAC 2018

By Brian Bailey - 28 Jun, 2018 - Comments: 0

Wednesday starts with a visionary talk followed by a keynote. The Visionary talk was given by Chidi Chidambaram, VP of engineering for Qualcomm, and looked at 'Challenges to Enable 5G System Scaling.' "We have to start taking a system view rather than just following technology and at the same time we have to get concerned about durability," he said. "Mobile will continue to be the leader becaus... » read more

Tuesday At DAC 2018

By Brian Bailey - 27 Jun, 2018 - Comments: 0

The morning starts with the Accellera Breakfast. Accellera has made some significant progress this year and we can expect to hear about the approval of the Portable Stimulus 1.0 specification later in the conference as well as the initial release of SystemC CCI as well as a proposal for the creation of an IP Security Assurance Working Group, which will discuss standards development to address s... » read more

Monday At DAC 2018

By Brian Bailey - 26 Jun, 2018 - Comments: 0

DAC #55 started with rumors flying. Will this be the last DAC as we know it? Is there a huge chasm forming between academia and the industry? Will DAC be able to make it in Las Vegas where there is no local interest? Of course, those who have been in the industry know that this kind of speculation happens every few years, and in the 80s, Las Vegas was a very popular location for DAC. There was ... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: DAC 2018

Wednesday At DAC 2018

Tuesday At DAC 2018

Monday At DAC 2018