Inside Chips Podcast: Data Movement In The AI Age


AI is all about data movement — lots of it. The key is to move data as little as possible, and when it is moved, to do it efficiently, securely, and blindingly fast. Semiconductor Engineering talks with Arteris CEO Charlie Janac in this one-on-one discussion about the impact of AI on networks on chip and what will change going forward. To listen to the podcast, click here. » read more

Speeding Up Die-To-Die Interconnectivity


Disaggregating SoCs, coupled with the need to process more data faster, is forcing engineering teams to rethink the electronic plumbing in a system. Wires don't shrink, and just cramming more wires or thicker wires into a package are not viable solutions. Kevin Donnelly, vice president of strategic marketing at Eliyan, talks about how to speed up data movement between chiplets with bi-direction... » read more

Data Movement Is the Energy Bottleneck of Today’s SoCs


In today’s AI-focused semiconductor landscape, raw compute performance alone no longer defines the effectiveness of a system-on-chip (SoC). The efficiency of data movement across the chip has become just as important. Whether designed for data centers or edge AI devices, SoCs must now prioritize data transport as a core architectural consideration. Moving data efficiently across the silicon f... » read more

What’s Changing In SerDes


SerDes is all about pushing data through the smallest number of physical channels. But when it comes to AI, more data needs to be moved, and it has to be moved more quickly. Todd Bermensolo, product marketing manager at Alphawave Semi, talks about the impact of faster data movement on the transmitter (more power) and on the receiver (gain and advanced equalization), how to ensure signal inte... » read more

Lines Blurring Between Supercomputing And HPC


Supercomputers and high-performance computers are becoming increasingly difficult to differentiate due to the proliferation of AI, which is driving huge performance increases in commercial and scientific applications and raising similar challenges for both. While the goals of supercomputing and high-performance computing (HPC) have always been similar — blazing fast processing — the mark... » read more

Scaling Performance In AI Systems


Improving performance in AI designs involves the usual tradeoffs in power and performance, but achieving a good balance is becoming much more challenging. There is more data to process, new heterogeneous architectures to contend with, and much higher utilization rates. Andy Nightingale, vice president of product management and marketing at Arteris, talks about where the bottlenecks are, how to ... » read more

Workload-Specific Data Movements Across AI Workloads in Multi-Chiplet AI Accelerators


A new technical paper titled "Communication Characterization of AI Workloads for Large-scale Multi-chiplet Accelerators" was published by researchers at Universitat Politecnica de Catalunya. Abstract "Next-generation artificial intelligence (AI) workloads are posing challenges of scalability and robustness in terms of execution time due to their intrinsic evolving data-intensive characteris... » read more

Higher Density, More Data Create New Bottlenecks In AI Chips


Data movement is becoming a bigger problem at advanced nodes and in advanced packaging due to denser circuitry, more physical effects that can affect the integrity of signals or the devices themselves, and a significant increase in data from AI and machine learning. Just shrinking features in a design is no longer sufficient, given the scaling mismatch between SRAM-based L1 cache and digital... » read more

The Journey To Exascale Computing And Beyond


High performance computing witnessed one of its most ambitious leaps forward with the development of the US supercomputer “Frontier.” As Scott Atchley from Oak Ridge National Laboratory discussed at Supercomputing 23 (SC23) in Denver last month, the Frontier had the ambitious goal of achieving performance levels 1000 times higher than the petascale systems that preceded it, while also stayi... » read more

Designing for Data Flow


Movement and management of data inside and outside of chips is becoming a central theme for a growing number of electronic systems, and a huge challenge for all of them. Entirely new architectures and techniques are being developed to reduce the movement of data and to accomplish more per compute cycle, and to speed the transfer of data between various components on a chip and between chips ... » read more

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