Billions And Billions Invested

By Mark LaPedus - 17 Apr, 2014 - Comments: 4

Over the years, next-generation [getkc id="80" kc_name="lithography"] (NGL) has suffered various setbacks and delays. But until recently, the industry basically shrugged its shoulders and expressed relatively little anxiety about the NGL delays. After all, optical lithography was doing the job in the fab and NGL would eventually materialize. Today, however, the mood is different. In fact, th... » read more

Directed Self-Assembly Gains Momentum

By Mark LaPedus - 20 Mar, 2014 - Comments: 0

At last year’s SPIE Advanced Lithography symposium, directed self-assembly (DSA) grabbed the spotlight as chipmakers provided the first glimpse of their initial work and results with the technology. The results were stunning, thereby propelling DSA from a curiosity item to a possible patterning solution for next-generation devices. Last year, in fact, GlobalFoundries, IBM, Intel and Sams... » read more

Mask Data Prep Issues Compounding At 20nm

By Ann Mutschler - 19 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler When it comes to mask data prep—the step in the design and manufacturing flow that occurs just after optical proximity correction (OPC)—challenges have continued to rise with the subsequent moves to smaller geometries. This is driven by the scaling demands of delivering about a 50% area shrink from node to node on a two-year cycle, and thus dictates the lithog... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Design 2 Silicon

Billions And Billions Invested

Directed Self-Assembly Gains Momentum

Mask Data Prep Issues Compounding At 20nm