tag: die-to-die interconnect

Die-to-die Interconnect Standards In Flux
By Bryon Moyer - 15 May, 2025 - Comments: 0

UCIe, a standard for die-to-die interconnect in advanced packages, has drawn concern about being too heavyweight with its 2.0 release. But the fact that many of the new features are optional seems to have been lost in much of the public discussion. In fact, new capabilities that support a possible future chiplet marketplace are not required for designs that don’t target that marketplace. ... » read more

Synchronous Die-to-Die Signaling Using Aeonic Connect
By Movellus - 26 Jul, 2023 - Comments: 0

This paper presents a system providing accurate clock alignment for on-die and die-to-die synchronous circuits. A low-frequency reference clock provides an accurate timing reference with low power consumption, while distributed delay lines align the endpoints of loosely constrained clock trees. For on-die clocks, this synchronization strategy severs the traditional relationship between power an... » read more

The Future Of Chiplet Reliability
By Nir Sever - 11 Jul, 2023 - Comments: 0

Chipmakers are increasingly turning to advanced packaging to overcome the reticle size limit of silicon manufacturing without increasing transistor density. This method also allows hybrid devices with dies in different process nodes while improving yield, which decreases exponentially with size. However, 2.5D/3D designs introduce a fair share of new challenges, one of the most significant be... » read more

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