Roundtable: ESL Grows As Processes Shrink

By Ed Sperling - 22 Feb, 2012 - Comments: 0

System-Level Design talks with Steve Bailey of Mentor Graphics, Michael (Mac) McNamara of Cadence Design Systems, Ghislain Kaiser of DOCEA Power and Shawn McCloud of Calypto about what will propel growth in the system-level design tools marketplace. [youtube vid=yBhLLN40mSE] » read more

Thinking Differently About Power

By Ed Sperling - 12 Jan, 2012 - Comments: 0

By Ed Sperling Battery life and lower electricity bills are now marketing tools for makers of SoCs, the mobile devices they go into, and servers that power data centers. A smart phone battery that lasts through the day without a charge, even when the user is playing high-action games, is a lot more attractive than one lasting only a few hours. And a data center electricity bill that shows a sh... » read more

Design For Power Methodology

By Ed Sperling - 21 Jul, 2011 - Comments: 0

By Ann Steffora Mutschler It is rare to find an advanced chip today that has not been designed considering power from the very earliest point. In fact, it is safe to say that power is the No. 1 priority, or a close No. 2. But to achieve the highest performance for a low-power design, a design-for-power methodology is necessary, comprised of the capabilities to implement power in the most ef... » read more

Building Up In 3D

By Ed Sperling - 18 Nov, 2010 - Comments: 0

By Ed Sperling Stacked die are expected to begin showing up in volume in late 2012 and in 2013, turning what has been a science experiment into a mainstream way of designing and manufacturing SoCs. This magnitude of this shift cannot be overstated, and clearly all of the pieces are not in place to make it all happen immediately. There also are significant technology challenges to overcome, ... » read more

Defining Reliability In Low-Power Designs

By Ed Sperling - 15 Oct, 2009 - Comments: 0

By Ann Steffora Mutschler Having a clear understanding of what reliability means for a particular low-power application can make a significant difference when it comes to communicating with engineering team members and customers. Is reliability simply a question of how long a device can run without errors? And what happens to reliability when power modeling, verification and other design tec... » read more

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Knowledge Centers
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A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

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3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

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Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

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The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

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Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

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tag: Docea Power

Roundtable: ESL Grows As Processes Shrink

Thinking Differently About Power

Design For Power Methodology

Building Up In 3D

Defining Reliability In Low-Power Designs