Characteristics and Potential HW Architectures for Neuro-Symbolic AI


A new technical paper titled "Towards Efficient Neuro-Symbolic AI: From Workload Characterization to Hardware Architecture" was published by researchers at Georgia Tech, UC Berkeley, and IBM Research. Abstract: "The remarkable advancements in artificial intelligence (AI), primarily driven by deep neural networks, are facing challenges surrounding unsustainable computational trajectories, li... » read more

Google’s TPU v4 Architecture: 3 Major Features


A new technical paper titled "TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings" was published by researchers at Google. Abstract: "In response to innovations in machine learning (ML) models, production workloads changed radically and rapidly. TPU v4 is the fifth Google domain specific architecture (DSA) and its third supercomputer f... » read more

RISC-V Disrupting EDA


The electronic design automation (EDA) industry started in the 1980s and primarily was driven by the test and PCB industries. The test industry was focused on simulation so that test vector sets could be developed and optimized. The PCB industry needed help managing complexity as system sizes grew. That complexity soon was eclipsed by IC complexity and the costs associated with making a mist... » read more