Optimizing EDA Cloud Hardware And Workloads

By Aharon Etengoff - 04 Mar, 2024 - Comments: 0

Optimizing EDA hardware for the cloud can shorten the time required for large and complex simulations, but not all workloads will benefit equally, and much more can be done to improve those that can. Tens of thousands of GPUs and specialized accelerators, all working in parallel, add significant and elastic compute horsepower for complex designs. That allows design teams to explore various a... » read more

IC Tool Vendors Eye Cloud-Native Future

By Aharon Etengoff - 25 Jan, 2024 - Comments: 0

The promise of scalability and efficiency is accelerating the migration of electronic design automation (EDA) to the cloud. Unlimited on-demand compute resources fundamentally change the chip design paradigm, where tools and workloads are no longer constrained by localized hardware. This is easier said than done, however. Optimizing existing tools and infrastructure, creating a new generatio... » read more

Navigating EDA Vendor Cloud Options

By Ann Mutschler - 25 Oct, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the challenges of cost-dependent cloud decisions, and how to navigate between different EDA vendor clouds options with Philip Steinke, fellow, CAD infrastructure and physical design at AMD; Mahesh Turaga, vice president of business development for cloud at Cadence Design Systems; Richard Ho, vice president hardware engineering ... » read more

Tradeoffs Between On-Premise And On-Cloud Design

By Ann Mutschler - 16 Aug, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down discuss how and why companies are dividing up work on-premise and in the cloud, and what to watch out for, with Philip Steinke, fellow, CAD infrastructure and physical design at AMD; Mahesh Turaga, vice president of business development for cloud at Cadence Design Systems; Richard Ho, vice president hardware engineering at Lightmatter; Cr... » read more

The Good And Bad Of Chip Design On Cloud

By Ann Mutschler - 27 Jul, 2023 - Comments: 0

Semiconductor Engineering sat down to talk about how the shift toward chip design on cloud has sped up, whether the benefits of cloud are realized in chip design, and some of the most pressing challenges to chip design on cloud today, with Philip Steinke, fellow, CAD infrastructure and physical design at AMD; Mahesh Turaga, vice president of business development for cloud at Cadence Design Syst... » read more

Made in the Cloud!

By Synopsys - 12 Apr, 2022 - Comments: 0

While software developers have been building and delivering software in the cloud for many years now, how much IC hardware is “made in the cloud”? We’re here to help you understand the case for IC hardware development in the cloud and answer the most common questions. Download the paper and learn: Why isn’t everybody doing it? Why cloud? Why now? Can you afford to ignore i... » read more

Rocky Road To Designing Chips In The Cloud

By Ann Mutschler - 24 Jun, 2021 - Comments: 0

EDA is moving to the cloud in fits and starts as tool vendors sort out complex financial models and tradeoffs while recognizing a potentially big new opportunity to provide unlimited processing capacity using a pay-as-you-go approach. By all accounts, a tremendous amount of tire-kicking is happening now as EDA vendors and users delve into the how and why of moving to the cloud for chip desig... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer