tag: eSilicon

Using Memory Differently To Boost Speed
By Ed Sperling - 22 Jul, 2019 - Comments: 2

Boosting memory performance to handle a rising flood of data is driving chipmakers to explore new memory types and different ways of using existing memory, but it also is creating some complex new challenges. For most of the semiconductor design industry, memory has been a non-issue for the past couple of decades. The main concerns were price and size, but memory makers have been more than a... » read more

Will In-Memory Processing Work?
By Brian Bailey - 16 Jul, 2019 - Comments: 1

The cost associated with moving data in and out of memory is becoming prohibitive, both in terms of performance and power, and it is being made worse by the data locality in algorithms, which limits the effectiveness of cache. The result is the first serious assault on the von Neumann architecture, which for a computer was simple, scalable and modular. It separated the notion of a computatio... » read more

Big Shifts In Big Data
By Ed Sperling - 09 Jul, 2019 - Comments: 0

The big data market is in a state of upheaval as companies begin shifting their data strategies from "nothing" or "everything" in the cloud to a strategic mix, squeezing out middle-market players and changing what gets shared, how that data is used, and how best to secure it. This has broad implications for the whole semiconductor supply chain, because in many cases it paves the way for ... » read more

Edge Complexity To Grow For 5G
By Kevin Fogarty and Ed Sperling - 02 Jul, 2019 - Comments: 0

Edge computing is becoming as critical to the success of 5G as millimeter-wave technology will be to the success of the edge. In fact, it increasingly looks as if neither will succeed without the other. 5G networks won’t be able to meet 3GPP’s 4-millisecond-latency rule without some layer to deliver the data, run the applications and broker the complexities of multi-tier Internet apps ac... » read more

Machine Learning Inferencing Moves To Mobile Devices
By Kevin Fogarty - 02 Jul, 2019 - Comments: 0

It may sound retro for a developer with access to hyperscale data centers to discuss apps that can be measured in kilobytes, but the emphasis increasingly is on small, highly capable devices. In fact, Google staff research engineer Pete Warden points to a new app that uses less than 100 kilobytes for RAM and storage, creates an inference model smaller than 20KB, and which is capable of proce... » read more

Google Cloud—A View From The Top
By Mike Gianfagna - 27 Jun, 2019 - Comments: 0

I recently had the opportunity to attend a retreat-style event in Napa Valley hosted by the Google Cloud team. Like many such events I’ve attended over the years, the guests were treated to excellent accommodations, fabulous food, a good amount of free time for networking or to partake in activities, relevant and on-point presentations and world-class wine (this is Napa Valley after all). All... » read more

Test Chips Play Larger Role At Advanced Nodes
By Ann Mutschler - 27 Jun, 2019 - Comments: 0

Test chips are becoming more widespread and more complex at advanced process nodes as design teams utilize early silicon to diagnose problems prior to production. But this approach also is spurring questions about whether this approach is viable at 7nm and 5nm, due to the rising cost of prototyping advanced technology, such as mask tooling and wafer costs. Semiconductor designers have long b... » read more

CEO Outlook: Rising Costs, Chiplets, And A Trade War
By Ed Sperling - 26 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss what's changing across the semiconductor industry with Wally Rhines, CEO emeritus at Mentor, a Siemens Business; Jack Harding, president and CEO of eSilicon; John Kibarian, president and CEO of PDF Solutions; and John Chong, vice president of product and business development for Kionix. What follows are excerpts of that discussion, which was held in... » read more

Power, Reliability And Security In Packaging
By Ed Sperling - 19 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with Ajay Lalwani, vice president of global manufacturing operations at eSilicon; Vic Kulkarni, vice president and chief strategist in the office of the CTO at ANSYS; Calvin Cheung, vice president of engineering at ASE; Walter Ng, vice president of business management at UMC; and Tien Shiah, senior manager for memory at Samsun... » read more

Waiting For Chiplet Interfaces
By Brian Bailey - 13 Jun, 2019 - Comments: 0

There aren't many success stories related to chiplets today for a very simple reason—there are few standard interfaces defined for how to connect them. In fact, the only way to use them is to control both sides of the interface with a proprietary interface and protocol. The one exception is the definition of HBM2, which enables large quantities of third-party DRAM to be connected to a logi... » read more

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