Week In Review: Manufacturing, Test

By Mark LaPedus - 04 Mar, 2022 - Comments: 0

Packaging ASE, AMD, Arm, Google, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC have announced the formation of a consortium that will establish a die-to-die interconnect standard and foster an open chiplet ecosystem. The founding companies also ratified the UCIe specification, an open industry standard developed to establish a standard interconnect at the package level. The UCIe 1.0 s... » read more

Manufacturing Bits: July 20

By Mark LaPedus - 20 Jul, 2021 - Comments: 0

Interference EUV lithography ESOL has developed a standalone interference extreme ultraviolet (EUV) lithography tool for use in R&D applications. The system, called EMiLE (EUV Micro-interference Lithography Equipment), is primary used to speed up the development of EUV photoresists and related wafer processes. The system is different than ASML’s EUV lithography scanners, which are ... » read more

Finding Defects In EUV Masks

By Mark LaPedus - 23 Jan, 2020 - Comments: 0

Extreme ultraviolet (EUV) lithography is finally in production at advanced nodes, but there are still several challenges with the technology, such as EUV mask defects. Defects are unwanted deviations in chips, which can impact yield and performance. They can crop up during the chip manufacturing process, including the production of a mask or photomask, sometimes called a reticle. Fortunately... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: ESOL

Week In Review: Manufacturing, Test

Manufacturing Bits: July 20

Finding Defects In EUV Masks