Is EUV Making Progress?

By Ann Mutschler - 18 Jun, 2015 - Comments: 4

By Ann Steffora Mutschler & Ed Sperling EUV has been promised for a couple of decades, counted on for at least three process nodes on the ITRS roadmap, and considered essential to chip manufacturing since 22nm. Billions of dollars have been invested in R&D, engineering teams from around the world have contributed to its development, and still serious problems persist. Just how close... » read more

Not All Scientific Problems Can Be Solved

By Ed Sperling - 18 Jun, 2015 - Comments: 0

In the early part of the 20th century psychologist Karl Lashley set out to locate and study the engram, the memory storage center for the human brain. He never found it. In fact, he ended up disproving the theory that an engram even exists, which was far more important to the understanding of the brain than if he had proven the existence of an engram. The results of more than six decades of ... » read more

Speeding Up E-beam Inspection

By Mark LaPedus - 18 Jun, 2015 - Comments: 0

Wafer inspection, the science of finding killer defects in chips, is reaching a critical juncture. Optical inspection, the workhorse technology in the fab, is being stretched to the limit at advanced nodes. And e-beam inspection can find tiny defects, but it remains slow in terms of throughput. So to fill the gap, the industry has been working on a new class of multiple beam e-beam inspectio... » read more

SoC Integration Headaches Grow

By Ed Sperling - 16 Jun, 2015 - Comments: 0

As the number of IP blocks grows, so do the headaches of integrating the various pieces and making sure they perform as planned within a prescribed power envelope. This is easier said than done, particularly at the most advanced process nodes. There are more blocks, more power domains, more states and use-model dependencies, and there is much more contention for memories. There are physical ... » read more

Manufacturing Bits: June 16

By Mark LaPedus - 16 Jun, 2015 - Comments: 0

Harmonic EUV The U.S. Department of Energy’s Lawrence Berkeley National Laboratory has devised an efficient extreme ultraviolet (EUV) source. The technology could one day be used for a new class of metrology tools, based on angle-resolved photoemission spectroscopy (ARPES). This technique makes use of a photoelectric effect for studying materials. To enable the source, Berkeley Labs devel... » read more

The Week In Review: Manufacturing

By Mark LaPedus - 12 Jun, 2015 - Comments: 0

Christopher Rolland, an analyst at FBR, made a startling statement in a recent report. “At the pace of consolidation set thus far this year, 32% of all U.S. publicly traded semiconductor companies would be acquired in 2015! While this run-rate is not likely sustainable and should slow as the year progresses, we still expect ~15% consolidation rates for the remainder of this cycle (above low-t... » read more

What’s Different At 16/14nm?

By Ed Sperling - 28 May, 2015 - Comments: 0

Will finFETs live up to their promise? It depends on whom you ask, when you ask that question, and the intended application of a design. But across the semiconductor industry, there is general agreement that it's getting easier to work at the most advanced nodes as tools and flows are better understood and overall experience increases. There is no question that [getkc id="185" kc_name="finFE... » read more

Manufacturing Bits: May 26

By Mark LaPedus - 26 May, 2015 - Comments: 0

Table-top EUV Swinburne University of Technology has developed a table-top extreme ultraviolet (EUV) laser power source. The source could be used to develop a system for use in metrology and other applications. The table-top setup is a new way to generate bright beams of coherent EUV radiation. It may offer a cost-effective alternative to large-scale facilities, such as synchrotrons or free... » read more

10nm Fab Challenges

By Mark LaPedus - 21 May, 2015 - Comments: 1

After a promising start in 2015, the semiconductor equipment industry is currently experiencing a slight lull. The pause is expected to be short-lived, however. Suppliers of [getkc id="208" comment="3D NAND"] devices are expected to add more fab capacity later this year. And about the same time, foundries are expected to order the first wave of high-volume production tools for 10nm. At 10nm... » read more

The Roadmap To 5nm

By SEMI - 11 May, 2015 - Comments: 0

By Debra Vogler Among the challenges the semiconductor industry will be facing as it moves down the path to node 5 are resistance-capacitance (RC) management and integration. SEMI is pleased to announce a SEMICON West 2015 STS technical program exploring these and other high-volume manufacturing challenges. According to An Steegen, SVP of Process Technology at imec, the list of RC managemen... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?