K-Fault Resistant Partitioning To Assess Redundancy-Based HW Countermeasures To Fault Injections

A technical paper titled “Fault-Resistant Partitioning of Secure CPUs for System Co-Verification against Faults” was published by researchers at Université Paris-Saclay, Graz University of Technology, lowRISC, University Grenoble Alpes, Thales, and Sorbonne University. Abstract: "To assess the robustness of CPU-based systems against fault injection attacks, it is necessary to analyze the... » read more

Hardware-Efficient Approach To Defend Against Fault Attacks

A technical paper titled "Fault Attacks on Access Control in Processors: Threat, Formal Analysis and Microarchitectural Mitigation" was published by researchers at University of Kaiserslautern-Landau. Abstract: "Process isolation is a key component of the security architecture in any hardware/software system. However, even when implemented correctly and comprehensively at the software (SW) le... » read more

Quantum Machine Learning: Security Threats & Lines Of Defense

New research paper from Pennsylvania State University explores quantum machine learning (QML) and its use in hardware security. Find the technical paper here. April 2022. Satwik Kundu and Swaroop Ghosh. 2022. Security Aspects of Quantum Machine Learning: Opportunities, Threats and Defenses (Invited). In Proceedings of the Great Lakes Symposium on VLSI 2022 (GLSVLSI ’22), June 6–8,... » read more

Verifying Side-Channel Security Pre-Silicon

As security grows in importance, side-channel attacks pose a unique challenge because they rely on physical phenomena that aren’t always modeled for the design verification process. While everything can be hacked, the goal is to make it so difficult that an attacker concludes it isn't worth the effort. For side-channel attacks, the pre-silicon design is the best place to address any known ... » read more

Scaling Anti-Tamper Protection To Meet Escalating Threats

Anti-tamper tends to be one of those catchall phrases encompassing any countermeasure on a security chip. A more precise definition would be that anti-tamper protection is any collection of countermeasures that serves to thwart an adversary’s attempt to monitor or affect the correct operation of a chip or a security core within a chip. Given that, it can be useful to think about a hierarchy o... » read more

FIAs Pose Tricky Security Attacks

Voltage and clock glitching are terms crowding into the emerging lexicon of chip security attacks. These are two popular methods adversaries use that can be categorized under the umbrella of fault injection attacks (FIAs). Micro-architectural vulnerabilities like Meltdown, Spectre, Foreshadow and Spoiler have been in the limelight for months. But now, FIAs are getting more attention as the indu... » read more