Better Code With RTL Linting And CDC Verification

By Sergei Zaychenko - 23 Feb, 2017 - Comments: 0

Automated design rule checking, or linting, has been around in RTL verification for at least a couple decades, yet still many HDL designers completely ignore this simple yet very powerful bug hunting method. Why would a busy designer need to run this annoying warning generator? The hostility against using conventional linting tools is often explained by the enormous amount of output noise, limi... » read more

Power Limits Of EDA

By Brian Bailey - 13 Oct, 2016 - Comments: 3

Power has become a major gating factor in semiconductor design. It is now the third factor in design optimization, along with performance, and is almost becoming more important than area. But there are limits to the amount of help that [getkc id="7" kc_name="EDA"] can provide with [getkc id="106" kc_name="power optimization"]. Power is not just an optimization problem. It is a design problem... » read more

Microarchitecture Design For Low Power

By Anand Iyer - 14 May, 2015 - Comments: 0

As designs move to finFET process nodes, dynamic power reduction has become a requirement. Designers have to eliminate or minimize all sources of redundant switching activity in order to reduce dynamic power in the design. In our last blog, we looked at dynamic power wastage due to redundant adders and multipliers and how to gate these operators to save power. We also mentioned a couple of m... » read more

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Better Code With RTL Linting And CDC Verification

Power Limits Of EDA

Microarchitecture Design For Low Power

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