FIR And Median Filter Accelerators In CodAL

By Codasip - 25 Oct, 2023 - Comments: 0

5G is the latest generation of cellular networks using the 3rd Generation Partnership Project (3GPP) 5G New Radio air interface. Unlike previous generations of network (2G, 3G & 4G) which had a one-size-fits-all approach, 5G aims to address a wide range of very different applications. To flexibly support diverse quality of service requirements, network slicing is introduced to enable mul... » read more

Integrating 16nm FPGA Into 28/22nm SoC Without Losing Speed Or Flexibility

By Geoff Tate - 05 Jan, 2023 - Comments: 0

Systems companies like FPGA because it gives parallel processing performance that can outdo processors for many workloads and because it can be reconfigured when standards, algorithms, protocols or customer requirements change. But FPGAs are big, burn a lot of power and are expensive. Customers would like to integrate them into their adjacent SoC if possible. Dozens of customers are now u... » read more

Formal Verification Of AI Processor Datapaths In Automotive Applications

By Laureano Carrasco - 05 Jan, 2023 - Comments: 0

There aren’t many electronic applications that require correctness, safety, and security more than automobiles and other road vehicles. Owners rely on their cars operating properly and reliably at all times. The very lives of drivers, passengers, and those nearby are at risk if a vehicle misbehaves. The situation grows more serious with every innovation in automotive electronics. With a mo... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: FIR filter

FIR And Median Filter Accelerators In CodAL

Integrating 16nm FPGA Into 28/22nm SoC Without Losing Speed Or Flexibility

Formal Verification Of AI Processor Datapaths In Automotive Applications