Verification Scorecard: How Well Is The Industry Doing?

By Brian Bailey - 25 Aug, 2022 - Comments: 0

Semiconductor Engineering sat down to discuss how well verification tools and methodologies have been keeping up with demand, with Larry Lapides, vice president of sales for Imperas Software; Mike Thompson, director of engineering for the verification task group at OpenHW; Paul Graykowski, technical marketing manager for Arteris IP; Shantanu Ganguly, vice president of product marketing at Caden... » read more

Who Does Processor Validation?

By Brian Bailey - 27 Jun, 2022 - Comments: 1

Defining what a processor is, and what it is supposed to do, is not always as easy as it sounds. In fact, companies are struggling with the implications of hundreds of heterogenous processing elements crammed into a single chip or package. Companies have extensive verification methodologies, but not for validation. Verification is a process of ensuring that an implementation matches a specif... » read more

The Third Generation Of FPGA Prototyping

By Robert Parris - 22 Dec, 2021 - Comments: 0

Bench setups with physical prototypes lie at the very heart of electrical and electronic engineering. With all due respect to the many powerful forms of modeling and simulation, at some point the engineering team wants to work with hardware. When a system is built entirely from existing components, it is possible to build a prototype of the product as soon as it has been designed. When the desi... » read more

Continuous Integration For Digital Design

By Christian Skubich - 17 Dec, 2021 - Comments: 0

By Christian Skubich and Nico Peter In 2001, the Manifesto for Agile Software Development [1] laid the foundation for many modern software development processes. Today, 20 years later, agile methods are in widespread use in numerous domains. Out of the participants in the study Status Quo (Scaled) Agile 2020 [2], only 9% still relied on classic project management methods. One core element... » read more

What’s Next For Emulation

By Brian Bailey - 28 Oct, 2021 - Comments: 1

Emulation is now the cornerstone of verification for advanced chip designs, but how emulation will evolve to meet future demands involving increasingly dense, complex, and heterogeneous architectures isn't entirely clear. EDA companies have been investing heavily in emulation, increasing capacity, boosting performance, and adding new capabilities. Now the big question is how else they can le... » read more

FPGA Prototyping: Supersizing Scale And Performance

By Synopsys - 11 May, 2021 - Comments: 0

Given the cost of re-spinning a system-on-chip (SoC), semiconductor companies have always looked for ways to verify and validate the SoC before tape-out. Prototyping using field programmable gate arrays (FPGAs) became a key methodology as part of this pre-silicon verification and validation effort. Click here to read more. » read more

Verification’s Inflection Point

By Brian Bailey - 14 Jan, 2021 - Comments: 0

Functional verification is nearing an inflection point, brought on by rising complexity and the many tentacles that are intermixing it with other disciplines. New abstractions or different ways to approach the problems are needed. Being a verification engineer is no longer enough, except for those whose concerns is block-level verification. Most of the time and effort spent in verification i... » read more

The Increasingly Ordinary Task Of Verifying RISC-V

By Ann Mutschler - 03 Jun, 2020 - Comments: 0

As RISC-V processor development matures and its usage in SoCs and microcontrollers grows, engineering teams are starting to look beyond the challenges of the processor core itself. So far, the majority of industry verification efforts have focused on ISA compliance to standardize the RISC-V core. Now the focus is shifting to be how to handle verification as the system grows, especially as this... » read more

FPGA Prototyping Complexity Rising

By Ann Mutschler - 28 May, 2020 - Comments: 0

Multi-FPGA prototyping of ASIC and SoC designs allows verification teams to achieve the highest clock rates among emulation techniques, but setting up the design for prototyping is complicated and challenging. This is where machine learning and other new approaches are beginning to help. The underlying problem is that designs are becoming so large and complex that they have to be partitioned... » read more

Practical Processor Verification

By Brian Bailey - 23 Apr, 2020 - Comments: 0

Custom processors are making a resurgence, spurred on by the early success of the RISC-V ISA and the ecosystem that is rapidly building around it. But this shift is amid questions about whether processor verification has become a lost art. Years ago custom processors were common. But as the market consolidated around a handful of companies, so did the tools and expertise needed to develop th... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?