tag: Fraunhofer IIS EAS

Wrestling With Analog At 3nm
By Brian Bailey - 09 Sep, 2021 - Comments: 0

Analog engineers are facing big challenges at 3nm, forcing them to come up with creative solutions to a widening set of issues at each new process node. Still, these problems must be addressed, because no digital chip will work without at least some analog circuitry. As fabrication technologies shrink, digital logic improves in some combination of power, performance, and area. The process te... » read more

Tradeoffs Between Edge Vs. Cloud
By Brian Bailey - 09 Sep, 2021 - Comments: 0

Increasing amounts of processing are being done on the edge, but how the balance will change between what's computed in the cloud versus the edge remains unclear. The answer may depend as much on the value of data and other commercial reasons as on technical limitations. The pendulum has been swinging between doing all processing in the cloud to doing increasing amounts of processing at the ... » read more

Will Monolithic 3D DRAM Happen?
By Bryon Moyer - 09 Sep, 2021 - Comments: 1

As DRAM scaling slows, the industry will need to look for other ways to keep pushing for more and cheaper bits of memory. The most common way of escaping the limits of planar scaling is to add the third dimension to the architecture. There are two ways to accomplish that. One is in a package, which is already happening. The second is to sale the die into the Z axis, which which has been a to... » read more

An 8 Bit To 12 Bit Resolution Programmable 5 MSample/s Current Steering Digital-To-Analog Converter In A 22 nm FD-SOI CMOS Technology
By Fraunhofer IIS/EAS - 08 Sep, 2021 - Comments: 0

Authors: Jeongwook Koh, Division Engineering of Adaptive Systems EAS, Fraunhofer Institute for Integrated Circuits IIS, Dresden, Germany Shishira S. Venkatesha, Dresden University of Technology, Dresden, Germany Sunil S. Rao, Division Engineering of Adaptive Systems EAS, Fraunhofer Institute for Integrated Circuits IIS, Dresden, Germany Marcel Jotschke, Division Engineering of Ad... » read more

Analyzing Electro-Photonic Systems
By Brian Bailey - 30 Aug, 2021 - Comments: 1

The design and analysis of electro-optical systems is pushing tools into the complex multi-physics domain, making it challenging to create models that execute at reasonable cost — especially when they include thermal impacts. The lack of models and standards also is slowing the progression of the technology. Still the advantages are worth it to those willing to make the investment. Trad... » read more

Modeling Chips From Atoms To Systems
By Ann Mutschler - 26 Aug, 2021 - Comments: 1

Complexity in hardware design is spilling over to other disciplines, including software, manufacturing, and new materials, creating issues for how to model more data at multiple abstraction levels. Challenges are growing around which abstraction level to use for a particular stage of the design, when to use it, and which data to include. Those decisions are becoming more difficult at each ne... » read more

Week In Review: Design, Low Power
By Jesse Allen - 20 Aug, 2021 - Comments: 0

Tools Cadence teamed up with Tower Semiconductor to release a silicon-validated SP4T RF SOI switch reference design flow using the Cadence Virtuoso Design Platform and RF Solution. The reference design flow targets advanced 5G wireless, wireline infrastructure, and automotive IC product development and include a set of mixed-signal and RF design, simulation, system analysis and signoff tools t... » read more

Impact Of GAA Transistors At 3/2nm
By Brian Bailey - 16 Aug, 2021 - Comments: 2

The chip industry is poised for another change in transistor structure as gate-all-around (GAA) FETs replace finFETs at 3nm and below, creating a new set of challenges for design teams that will need to be fully understood and addressed. GAA FETs are considered an evolutionary step from finFETs, but the impact on design flows and tools is still expected to be significant. GAA FETs will offer... » read more

Condition Monitoring Of Drive Trains By Data Fusion Of Acoustic Emission And Vibration Sensors
By Fraunhofer IIS/EAS - 13 Aug, 2021 - Comments: 0

Early damage detection and classification by condition monitoring systems is crucial to enable predictive maintenance of manufacturing systems and industrial facilities. The data analysis can be improved by applying machine learning algorithms and fusion of data from heterogenous sensors. This paper presents an approach for a step-wise integration of classifications gained from vibration and ac... » read more

Adding Circuit Aging To Variability
By Brian Bailey - 12 Aug, 2021 - Comments: 0

Moving to a smaller node usually means another factor becomes important. The industry has become accustomed to doing process, temperature, voltage (PVT) corner analysis, but now it has to add aging into that mix. The problem is that planning for circuit aging is no longer a purely statistical process. Aging is dependent on activity over the lifetime of the device. Tools need to be modified a... » read more

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