tag: gate all around

Research Bits: Mar. 25
By Jesse Allen - 25 Mar, 2025 - Comments: 0

2D materials in 3D transistors Researchers at the University of California Santa Barbara investigated 3D gate-all-around (GAA) transistors made using 2D semiconductors. They considered three different approaches to channel stacking: nano-sheet FETs, nano-fork FETs, and nano-plate FETs. The nano-plate FET architecture, which exploits lateral stacking of 2D layers, was found to maximize the g... » read more

Demonstration Of An ALD IWO Channel In A GAA Nanosheet FET Structure (Georgia Tech, Micron)
By Technical Paper Link - 14 Feb, 2025 - Comments: 0

A new technical paper titled "First Demonstration of High-Performance and Extremely Stable W-Doped In2O3  Gate-All-Around (GAA) Nanosheet FET" was published by researchers at Georgia Institute of Technology and Micron. Abstract "We demonstrate a gate-all-around (GAA) nanosheet FET featuring an atomic layer-deposited (ALD) tungsten (W)-doped indium oxide (In2O3), or indium tungsten oxide ... » read more

Simulation Study Of Vertically Stacked 2D NSFETs
By Technical Paper Link - 12 Feb, 2025 - Comments: 0

A new technical paper titled "Simulation of Vertically Stacked 2-D Nanosheet FETs" was published by researchers at Università di Pisa and TU Wien. Abstract "We present a simulation study of vertically stacked 2-D nanosheet field-effect transistors (NSFETs). The aim of this investigation is to assess the performance and potential of FinFET alternatives, i.e., gate-all-around (GAA) nanosheet... » read more

TCAD Simulation Challenges For Gate-All-Around Transistors
By Victor Moroz - 17 Dec, 2024 - Comments: 0

By Victor Moroz and Shela Aboud The transition from finFET technology to Gate-All-Around (GAA) technology helps to reduce transistor variability and resume channel length scaling. It also brings several new challenges in terms of transistor design that need to be addressed. One of the challenges is handling the thin Si layers that come with GAA technology, where Si channel thickness scale... » read more

Models for Both Strained and Unstrained GAA FETs Using Neural Networks
By Technical Paper Link - 23 Sep, 2024 - Comments: 0

A new technical paper titled "Impact of Strain on Sub-3 nm Gate-all-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach" was published by researchers at Hanyang University and Alsemy Inc. Abstract "Impact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. The model was trained using 3D... » read more

How To Get The Most Out Of Gate-All-Around Designs
By Andrew Appleby - 25 Apr, 2024 - Comments: 0

The semiconductor industry has relied on finFETs, three-dimensional field-effect transistors with thin vertical fins, for many generations of technology. However, the industry is reaching the limits of how much finFETs can be shrunk while maintaining their speed and power benefits, which are crucial for artificial intelligence (AI) and machine learning (ML) applications. The solution is the gat... » read more

Reimagining PVT Monitoring IP For Advanced Node GAA Process
By Rohan Bhatnagar - 09 Apr, 2024 - Comments: 0

As process technology continues to evolve, so must design tools and the IP that support them. One example of an industry evolution is on the PVT monitoring IP side. The process, voltage, and temperature (PVT) monitors embedded within chips provide feedback on silicon status at every stage of the lifecycle, including mission use in the field. The data gathered from the monitors enables benefits ... » read more

Innovations in Device Design of The Gate-All-Around (GAA) Nanosheet FETs (IBM Research)
By Technical Paper Link - 23 Mar, 2023 - Comments: 0

A technical paper titled "A Review of the Gate-All-Around Nanosheet FET Process Opportunities" was published by researchers at IBM Research Albany. Abstract: "In this paper, the innovations in device design of the gate-all-around (GAA) nanosheet FET are reviewed. These innovations span enablement of multiple threshold voltages and bottom dielectric isolation in addition to impact of channel... » read more

Define & Grow III–V Vertical Nanowires At A High Footprint Density on a Si Platform
By Technical Paper Link - 29 Jul, 2022 - Comments: 0

New technical paper titled "Directed Self-Assembly for Dense Vertical III–V Nanowires on Si and Implications for Gate All-Around Deposition" is published from researchers at Lund University in Sweden. Abstract: "Fabrication of next generation transistors calls for new technological requirements, such as reduced size and increased density of structures. Development of cost-effective proc... » read more

FEOL Nanosheet Process Flow & Challenges Requiring Metrology Solutions (IBM Watson)
By Technical Paper Link - 08 Jul, 2022 - Comments: 0

New technical paper titled "Review of nanosheet metrology opportunities for technology readiness," from researchers at IBM Thomas J. Watson Research Ctr. (United States). Abstract (partial): "More than previous technologies, then, nanosheet technology may be when some offline techniques transition from the lab to the fab, as certain critical measurements need to be monitored in real time. T... » read more

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