Modeling Analytics for Computational Storage

By Samsung - 16 Feb, 2023 - Comments: 0

This paper discusses the expected performance benefits of offloading some important basic database operations — namely Scan, Filter and Project — to computational storage. We evaluate the performance estimate model using TPC-DS workload and two database engines running on Hadoop clusters: SPARK- SQL and Presto. This paper is organized as follows: after covering previous computational sto... » read more

Addressing Pain Points In Chip Design

By Ed Sperling - 13 Nov, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the impact of multi-physics and new market applications on chip design with John Lee, general manager and vice president of ANSYS' Semiconductor Business Unit; Simon Burke, distinguished engineer at Xilinx, Duane Boning, professor of electrical engineering and computer science at MIT; and Thomas Harms, director EDA/IP Alliance at Infineon. What foll... » read more

Changes In Data Storage and Usage

By Ed Sperling - 09 Oct, 2019 - Comments: 0

Doug Elder, vice president and general manager of OptimalPlus, talks about what’s changing in the storage and collection, including using data lakes and data engineering to break down silos and get data into a consistent format, and why it’s essential to define data up front based upon how quickly it needs to be accessed, as well as who actually owns the data. » read more

Solving The Memory Bottleneck

By Brian Bailey - 04 Oct, 2019 - Comments: 4

Chipmakers are scrambling to solve the bottleneck between processor and memory, and they are turning out new designs based on different architectures at a rate no one would have anticipated even several months ago. At issue is how to boost performance in systems, particularly those at the edge, where huge amounts of data need to be processed locally or regionally. The traditional approach ha... » read more

Big Shifts In Big Data

By Ed Sperling - 09 Jul, 2019 - Comments: 0

The big data market is in a state of upheaval as companies begin shifting their data strategies from "nothing" or "everything" in the cloud to a strategic mix, squeezing out middle-market players and changing what gets shared, how that data is used, and how best to secure it. This has broad implications for the whole semiconductor supply chain, because in many cases it paves the way for ... » read more

Searching For A System Abstraction

By Brian Bailey - 28 Jun, 2018 - Comments: 3

Without abstraction, advances in semiconductor design would have stalled decades ago and circuits would remain about the same size as analog blocks. No new abstractions have emerged since the 1990s that have found widespread adoption. The slack was taken up by IP and reuse, but IP blocks are becoming larger and more complex. Verification by isolation is no longer a viable strategy at the system... » read more

Shifting Performance Bottlenecks Driving Change In Chip And System Architectures

By Steven Woo - 14 Jan, 2016 - Comments: 0

The rise of personal computing in the 1980s — along with graphical user interfaces (GUIs) and applications ranging from office apps to databases — drove the demand for faster chips capable of removing processing bottlenecks and delivering a more responsive end-user experience. Indeed, the semiconductor industry has certainly come quite a long way since IBM launched its PC way back in 1981. ... » read more

One On One: John Lee

By Ed Sperling - 14 Jan, 2016 - Comments: 0

John Lee, general manager and vice president of Ansys—and the former CEO of data analytics firm Gear Design Solutions, which Ansys acquired in September—sat down with Semiconductor Engineering to talk about how big data techniques can be used in semiconductor and system design. What follows are excerpts of that conversation. SE: What's your goal now that Gear has been acquired by [getent... » read more

Integration Or Segregation

By Brian Bailey - 10 Sep, 2015 - Comments: 0

In the Electronics Butterfly Effect story, the observation was made that the electronics industry has gone non-linear, no longer supported by incremental density and cost-reducing improvements that Moore’s Law promised with each new node. Those incremental changes, over several decades, have meant that design and architecture have followed a predictable path with very few new ideas coming in ... » read more

Cloud 2.0

By Ed Sperling - 09 Jul, 2015 - Comments: 0

Corporate data centers are reluctant adopters of new technology. There is too much at stake to make quick changes, which accounts for a number of failed semiconductor startups over the past decade with better ideas for more efficient processors, not to mention rapid consolidation in other areas. But as the amount of data increases, and the cost of processing that data decreases at a slower rate... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?