Overview Of Security Verification Methodologies for SoC Designs Pre-Silicon (U. of Florida)


A technical paper titled "A Survey on SoC Security Verification Methods at the Pre-silicon Stage" was recently published by researchers at University of Florida. Abstract "This paper presents a survey of the state-of-the-art pre-silicon security verification techniques for System-on-Chip (SoC) designs, focusing on ensuring that designs, implemented in hardware description languages (HDLs) a... » read more

Comparison Of The Meta Modeling Approach With HGLs


A new technical paper titled "The Argument for Meta-Modeling-Based Approaches to Hardware Generation Languages" was published by researchers at Infineon Technologies and TU Munich. Abstract "The rapid evolution of Integrated Circuit (IC) development necessitates innovative methodologies such as code generation to manage complexity and increase productivity. Using the right methodology for g... » read more

System For Composing Hardware Generators (Cornell Univ.)


A technical paper titled “Correct and Compositional Hardware Generators” was published by researchers at Cornell University. Abstract: "Hardware generators help designers explore families of concrete designs and their efficiency trade-offs. Both parameterized hardware description languages (HDLs) and higher-level programming models, however, can obstruct composability. Different concrete ... » read more

Embedded FPGAs Going Mainstream?


Systems on chip have been made with many processing variants ranging from general-purpose CPUs to DSPs, GPUs, and custom processors that are highly optimized for certain tasks. When none of these options provide the necessary performance or consumes too much power, custom hardware takes over. But there is one type of processing element that has rarely been used in a major SoC— the [gettech id... » read more